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參數(shù)資料
| 型號： | MK68901 |
| 廠商： | 意法半導體 |
| 英文描述： | Multifunction Peripheral(多功能外圍電路) |
| 中文描述： | 多功能外圍（多功能外圍電路） |
| 文件頁數(shù)： | 15/33頁 |
| 文件大?。?/td> | 313K |
| 代理商： | MK68901 |
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Figure 18 :
Receiver StatusRegister (RSR).
BF :
Buffer Full. This bit is set when theinco-
ming word is transferred to the receive
buffer. The bit is cleared when the re-
ceive buffer is readby readingthe UDR.
Thisbit of theRSR is read only.
Overrun Error. This flag is set if the inco-
ming word is completely received and
duetobe tranferred tothereceive buf-fer,
butthelastwordinthereceive buf-ferhas
not yet been read. When this condition
occurs, the word in the receive buffer is
not overwritten by the new word. Note
that the status flags always reflect the
statusofthedataword currentlyin there-
ceive buffer. As such, the OE flag is not
actually set until the good word currently
inthe buffer has been read.Theinterrupt
associated with this error willalso not be
generateduntitheold wordinthereceive
buffer has been read.
OEflag iscleared byreading thereceiver
status register, and new data words can-
not be shifted to the receive buffer until
this is done.
Parity Error. This flag issetif thewordre-
ceived has a parity error. The flag is set
when the received word is tranferred
from the shift register to thereceive buf-
fer iftheerror condition exists.Theflag is
cleared when the nextword which does
nothave aparity error is tranferred to the
receive buffer.
Frame Error. Thisflagonly applies to the
asynchronous format. A frame error is
defined asa non-zero dataword which is
not followed by a stop bit. Like the PE
flag, theFE flagis set or cleared when a
word is transferred to the receivebuffer.
Found/Search. This combination control
bit and flag bit is only used with the syn-
chronous format. It can be set or cleared
bywritingtothisbitoftheRSR.Whenthis
bitis cleared, thereceiveris placed in the
search mode. In this mode, a bit by bit
comparison of the incoming data to the
OE:
PE :
FE :
F/S :
character in the SyncCharacter Register
(SCR) is made. The word length counter
is disabled. When a matchis found, this
bit will beset automatically, and theword
length counter will start as sync has not
been achieved. An interrupt will begene-
rated on the receive errorchannel when
the match occurs. The word just shifted
in will,or necessity, be equal to the sync
character, and itwillnot be transferred to
the receive buffer.
Break. This flag is used only when thea-
synchronous formatisselected. This flag
willbesetwhen anallzerodataword,fol-
lowedby nostop bit, is received. The flag
willstay set until both a non-zero bitis re-
ceived and the RSR has been read at
least once since the flag was set. Break
indicationwillnotoccurifthereceivebuff-
er is full.
Match/Character in Progress. If the syn-
chronous format is selected, this flag is
the Match flag.Itwillbeset each timethe
word transferred to the receive buffer
matchesthe sync character. It will be re-
set eachtime the word transferred to the
receive buffer does not match the sync
character. If the asynchronous format is
selected, this flag represents Character
in Progress. It willbe set upon a startbit
detectandclearedatthe endofthe word.
Sync Strip Enable. If this bit is set to a
one, data words that match the sync
character will not be loaded into the re-
ceive buffer, and no buffer full signal will
be generated.
Receiver Enable. This control bit is used
to enableordisable thereceiver. Ifa zero
is written to this bitof the RSR, the recei-
ver will turn off immediately. All flags in-
cluding theF/Sbitwill be cleared.Ifa one
is writtento this bit, normal receiver ope-
ration is enabled. The receive clock has
to be running before the receiver is en-
abled.
B :
M/CIP :
SS :
RE:
V000364
MK68901
15/33
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