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參數(shù)資料
| 型號： | MK68901 |
| 廠商： | 意法半導體 |
| 英文描述： | Multifunction Peripheral(多功能外圍電路) |
| 中文描述： | 多功能外圍（多功能外圍電路） |
| 文件頁數(shù)： | 2/33頁 |
| 文件大小： | 313K |
| 代理商： | MK68901 |
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necessary control and status interface to the pro-
grammer.
The MFP is a derivative of the MK3801 STI, a Z80
familyperipheral.
PIN DESCRIPTION
GND:
Ground
V
CC
:
+5 volts (
±
5%)
CS :
Chip Select (input, active, low). CS is u-
sed to selectthe MK68901 MFP for ac-
cesses to the internal registers. CS and
IACK must not be asserted at the same
time.
DS :
Data Strobe (input, active low). DS is u-
sedaspartofthechipselectandinterrupt
acknowledge functions.
R/W :
Read/Write (input). R/W is the signal
from the bus master indicating whether
thecurrent bus cycle is a Read (High) or
Write (Low) cycle.
DTACK : DataTransfer Acknowledge. (output, ac-
tive low, tri-stateable) DTACK is used to
signal thebus master that data is ready,
or that data has been accepted by the
MK68901 MFP.
A1-A5 :
Address Bus (inputs). The adress bus is
used to adress one of the internal regis-
ters during a reador write cycle.
D0-D7 :
Data Bus (bi-directional, tri-stateable).
Thedata busisused to receive datafrom
or transmit data to one of the internal re-
gisters during a read or write cycle. It is
also used to pass a vector during an in-
terrupt acknowledge cycle.
CLK :
Clock (input). This input is used to pro-
vide the internal timing for the MK68901
MFP.
RESET: Device reset. (input, active low). Reset
disables the USART receiver and trans-
mitter, stops all timers and forcesthe ti-
mer outputs low, disables all interrupt
channels and clears any pending inter-
rupts.The General Purpose Interrupt/I/O
lines will be placed in the tri-state input
mode.All internal registers (except the ti-
mer,USART data registers, and transmit
status register) will be cleared.
INTR :
Interrupt Request (output, active low, o-
pen drain). INTR is asserted when the
MK68901MFPisrequesting aninterrupt.
INTR is negated during an interrupt ac-
knowledge cycle or by clearing the pen-
ding interrupt(s) through software.
Interrupt Acknowledge (input, active
low).IACKisusedtosignaltheMK68901
MFP that the CPU is acknowledging an
interrupt. CS and IACk must not be as-
serted at the sametime.
Interrupt Enable In (input,active low). IEI
is used to signal the MK68901 MFP that
no higher priority device is requesting in-
terrupt service.
Interrupt Enable Out (output, active low).
IEO is used to signal lower priority peri-
pherals that neither the MK68901 MFP
nor another higher priority peripheral is
requesting interrupt service.
General Purpose Interrupt I/O lines.
These lines maybe used as interrupt in-
puts and/or I/O lines. When used as in-
terrupt inputs, their active edge is pro-
grammable. Adatadirection registerisu-
sed to define which lines are to be Hi-Z
inputsand which linesareto bepush-pull
TTL compatible outputs.
SerialOutput. This is the output ofthe U-
SART transmitter.
Serial Input. This is the input to the U-
SART receiver.
Receiver Clock. This input controls the
serial bit rate of theUSART receiver.
Transmitter Clock.Thisinputcontrolsthe
serial bit rate of theUSART transmitter.
Receiver Ready. (output, active low)
DMA output for receiver, which reflects
the status of Buffer Full in port number
15.
Transmitter Ready. (output, active low)
DMA output for transmitter, which re-
flects the status of Buffer Empty in port
number 16.
Timer Outputs. Each of the four timers
has an output which can produce a
square wave. The output will change
stateseach timercycle ; thusone fullpe-
riod of the timer out signalis equal to two
timer cycles. TAO or TBO can be reset
(logic ”O(jiān)”) by a write to TACR, or TBCR
respectively.
Timer Clock inputs. A crystal can be
connected between XTAL1 and XTAL2,
or XTAL1 can bedriven with a TTL level
clock.Whendriving XTAL1 withaTTLle-
IACK :
IEI :
IEO :
10-17 :
SO :
SI :
RC :
TC :
RR :
TR :
TAO,TBO,
TCO,TDO:
XTAL1,
XTAL2 :
MK68901
2/33
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