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參數(shù)資料
| 型號(hào)： | MPC2605ZP66R |
| 廠商： | MOTOROLA INC |
| 元件分類(lèi)： | SRAM |
| 英文描述： | Integrated Secondary Cache for PowerPC Microprocessors |
| 中文描述： | 32K X 72 CACHE TAG SRAM, 8.5 ns, PBGA241 |
| 封裝： | PLASTIC, BGA-241 |
| 文件頁(yè)數(shù)： | 16/30頁(yè) |
| 文件大?。?/td> | 288K |
| 代理商： | MPC2605ZP66R |
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MPC2605
16
MOTOROLA
MULTIPLE READ/WRITE HITS (NORMAL BUS MODE)
Figure 2 is an illustration of MPC2605 pipeline depth limit
with multiple read hits. The MPC2605 supports only one
level of address pipelining for data transfer. Therefore, it
must hold off on its assertion of AACK for a pipelined TS until
the data tenure for the first TS is done. The MPC2605
asserts AACK at the same time as the fourth TA for data
tenures that it controls.
CLK
CPU BG
TS
A0 – A31
TBST
L2 CLAIM
AACK
CPU DBG
DBB
TA
DH0 – DH31,
DL0 – DL31
1
2
3
4
5
6
7
8
9
10
11
A
B
C
A1
A2
A3
A4
B1
B2
B3
B4
Signal driven to the MPC2605
Signal driven by the MPC2605
High–Z
LEGEND
Figure 2. Multiple Burst Read (or Write) Hits
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