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參數(shù)資料
| 型號： | MPC2605ZP66R |
| 廠商： | MOTOROLA INC |
| 元件分類： | SRAM |
| 英文描述： | Integrated Secondary Cache for PowerPC Microprocessors |
| 中文描述： | 32K X 72 CACHE TAG SRAM, 8.5 ns, PBGA241 |
| 封裝： | PLASTIC, BGA-241 |
| 文件頁數(shù)： | 23/30頁 |
| 文件大?。?/td> | 288K |
| 代理商： | MPC2605ZP66R |
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MPC2605
23
MOTOROLA
READ HIT/WRITE HIT (WITHOUT CPU DBG PARKED)
Most of the previous examples have assumed CPU DBG
is asserted in the same cycle that the processor asserts TS.
This implies CPU DBG is parked. In some systems it may not
be desirable or possible to park CPU DBG. Figure 9 shows
the response for a read hit from the MPC2605 is gated by the
assertion of CPU DBG. The fastest response possible in a
system that does not park CPU DBG is 3–1–1–1.
1
2
3
4
5
6
7
A
A1
A2
A3
A4
CLK
TS
A0 – A31
TBST
L2 CLAIM
AACK
DBB
TA
DH0 – DH31,
DL0 – DL31
CPU BG
CPU DBG
Signal driven to the MPC2605
Signal driven by the MPC2605
High–Z
LEGEND
Figure 9. Burst Read (or Write) Hit Without CPU DBG Parked
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