參數(shù)資料
型號(hào): MPC2605ZP66R
廠商: MOTOROLA INC
元件分類(lèi): SRAM
英文描述: Integrated Secondary Cache for PowerPC Microprocessors
中文描述: 32K X 72 CACHE TAG SRAM, 8.5 ns, PBGA241
封裝: PLASTIC, BGA-241
文件頁(yè)數(shù): 19/30頁(yè)
文件大小: 288K
代理商: MPC2605ZP66R
MPC2605
19
MOTOROLA
WRITE THROUGH BURST WRITE HIT
Figure 5 shows the fastest possible burst write hit to a
write–through mode L2 cache line, read miss or write miss
processing that replaces a clean line. For these operations
MPC2605 will not assert any signals on the 60X bus. A
cache line is considered write through if WT is asserted by
the processor when it asserts TS.
The speed at which a write–through operation completes
is solely dependent on the memory controller. The timing
shown here assumes that the memory controller has a write
buffer that can accept data this quickly.
CLK
CPU BG
TS
A0 – A31
WT
L2 CLAIM
AACK
CPU DBG
DBB
TA
DH0 – DH31,
DL0 – DL31
1
2
3
4
5
6
A1
7
8
A
A2
A3
A4
TBST
Signal driven to the MPC2605
Signal driven by the MPC2605
High–Z
LEGEND
Figure 5. Fastest Possible Write Through Burst Write Hit for MPC603/604
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