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參數(shù)資料
| 型號： | MPC2605ZP66R |
| 廠商： | MOTOROLA INC |
| 元件分類： | SRAM |
| 英文描述： | Integrated Secondary Cache for PowerPC Microprocessors |
| 中文描述： | 32K X 72 CACHE TAG SRAM, 8.5 ns, PBGA241 |
| 封裝： | PLASTIC, BGA-241 |
| 文件頁數(shù)： | 27/30頁 |
| 文件大?。?/td> | 288K |
| 代理商： | MPC2605ZP66R |
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MPC2605
27
MOTOROLA
BOUNDARY SCAN ORDER
BIT NUMBER
The order of the boundary scan chain. Bit 0 is the closest
to TDO.
BIT/PIN NAME
The name of the physical pin. For an output enable cell,
this is the name of the corresponding output enable.
BIT/PIN TYPE
Input —
Input only pin.
I/O —
Bi–directional pin that can be put into high–Z state.
Output —
Output only pin.
Output Enable —
Boundary scan cell to hold the output
enable state of other I/O pads. Output enable does not
correspond to a physical pin. To set an I/O to an input, the
output enable must have a 1. To set an I/O to an output, the
output enable must have a 0. Note that these internal output
enables are active low.
Reserved –
This signal is reserved and must always be a 1.
OUTPUT ENABLE
The name of the output enable cell that determines if the
cell is enabled or in the high–Z state. If the pin type is input or
output enable, this entry will be empty.
Bit
Number
Bit/Pin Name
Bit/Pin
Type
Output
Enable
0
Reserved
Reserved
1
DL16
I/O
DOE
2
DL17
I/O
DOE
3
DL18
I/O
DOE
4
DL19
I/O
DOE
5
DL20
I/O
DOE
6
DL21
I/O
DOE
7
DL22
I/O
DOE
8
DL23
I/O
DOE
9
DP6
I/O
DOE
10
DL24
I/O
DOE
11
DL25
I/O
DOE
12
DL26
I/O
DOE
13
DL27
I/O
DOE
14
DL28
I/O
DOE
15
DL29
I/O
DOE
16
DL30
I/O
DOE
17
DL31
I/O
DOE
18
DP7
I/O
DOE
19
DH24
I/O
DOE
20
DH25
I/O
DOE
21
DH26
I/O
DOE
22
DH27
I/O
DOE
Bit
Number
Bit/Pin Name
Bit/Pin
Type
Output
Enable
23
DH28
I/O
DOE
24
DH29
I/O
DOE
25
DH30
I/O
DOE
26
DH31
I/O
DOE
27
DP3
I/O
DOE
28
DH16
I/O
DOE
29
DH17
I/O
DOE
30
DH18
I/O
DOE
31
DH19
I/O
DOE
32
DH20
I/O
DOE
33
DH21
I/O
DOE
34
DH22
I/O
DOE
35
DH23
I/O
DOE
36
DP2
I/O
DOE
37
L2 BG
Input
38
L2 MISS INH
Input
39
ABB
I/O
ABBOE
40
CPU3 DBG
Input
41
CPU3 BG
Input
42
CPU3 BR
Input
43
CPU2 DBG
Input
44
CPU2 BG
Input
45
CPU2 BR
Input
46
FDN
I/O
FDNOE
47
L2 DBG
Input
48
L2 BR
I/O
L2BROE
49
TA
I/O
TAOE
50
L2 CLAIM
Output
L2CLAIMOE
51
CPU DBG
Input
52
AACK
I/O
AACKOE
53
CI
I/O
AOE
54
ARTRY
I/O
ARTRYOE
55
WT
I/O
AOE
56
CPU BR
Input
57
TEA
Input
58
PWRDN
Input
59
DBB
I/O
DBBOE
60
HRESET
Input
61
TBST
I/O
AOE
62
TT0
I/O
AOE
63
TS
I/O
AOE
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