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參數(shù)資料
| 型號(hào)： | MPC2605ZP66R |
| 廠商： | MOTOROLA INC |
| 元件分類： | SRAM |
| 英文描述： | Integrated Secondary Cache for PowerPC Microprocessors |
| 中文描述： | 32K X 72 CACHE TAG SRAM, 8.5 ns, PBGA241 |
| 封裝： | PLASTIC, BGA-241 |
| 文件頁(yè)數(shù)： | 24/30頁(yè) |
| 文件大?。?/td> | 288K |
| 代理商： | MPC2605ZP66R |
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MPC2605
24
MOTOROLA
JTAG
AC OPERATING CONDITIONS AND CHARACTERISTICS
FOR THE TEST ACCESS PORT (IEEE 1149.1)
(TJ = 20 to + 110
°
C, Unless Otherwise Noted)
Input Timing Measurement Reference Level
Input Pulse Levels
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Input Rise/Fall Time
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
1.5 V
. . . . . . . . . . . . . . .
0 to 3.0 V
3 ns
Output Measurement Timing Level
Output Load
. . . . . . . . . . . . . . . . . . . . . . . .
1.5 V
. . . . . . . . . . . . . . . . . . . . . . .
50
Termination to 1.5 V
TAP CONTROLLER TIMING
Parameter
Symbol
b l
MPC2605–66
U i
Unit
Notes
Min
Max
Cycle Time
tCK
tCKH
tCKL
tA
tCKZ
tCKX
ts
tsd
30
—
ns
Clock High Time
12
—
ns
1
Clock Low Time
12
—
ns
1
Clock Low to Output Valid
5
9
ns
Clock Low to Output High–Z
0
9
ns
2
Clock Low to Output Active
0
9
ns
3, 4
Setup Times:
TMS
TDI
2
—
ns
1
Hold Times:
TMS
TDI
th
thd
2
—
ns
1
NOTES:
1. This parameter is sampled and not 100% tested.
2. TDO will High–Z from a clock low edge depending on the current state of the TAP state machine.
3. TDO is active only in the SHIFT–IR and SHIFT–DR state of the TAP state machine.
4. Transition is measured
±
500 mV from steady–state voltage. This parameter is sampled and not 100% tested.
TDI TEST
DATA IN
TCK TEST
CLOCK
tCK
TDO TEST
DATA OUT
tH
tCKX
tSD
tS
tHD
tA
tCKZ
TMS TEST
MODE SELECT
tCKH
tCKL
Figure 10. TAP Controller Timing
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