參數(shù)資料
型號(hào)： MPC2605ZP66R
廠商： MOTOROLA INC
元件分類(lèi)： SRAM
英文描述： Integrated Secondary Cache for PowerPC Microprocessors
中文描述： 32K X 72 CACHE TAG SRAM, 8.5 ns, PBGA241
封裝： PLASTIC, BGA-241
文件頁(yè)數(shù)： 17/30頁(yè)
文件大?。?/td> 288K
代理商： MPC2605ZP66R
MPC2605
17
MOTOROLA
READ MISS (NORMAL BUS MODE)
Figure 3 is an illustration of MPC2605 pipeline depth with a
read miss followed by a read hit.
For illustration purposes the read miss is shown as a
3–1–1–1 response from memory. AACK for the second
access is not driven true until the cycle after the fourth TA of
the read miss. This is because the MPC2605 is not in control
of TA for the first access and must, therefore, wait until the
first access’ data tenure is complete before it can drive AACK
true for the read hit.
CPU BG
TS
A0 – A31
TBST
L2 CLAIM
AACK
CPU DBG
DBB
TA
DH0 – DH31,
DL0 – DL31
CLK
1
2
3
4
5
6
7
8
9
10
11
12
A
B
A1
A2
A3
A4
B1
B2
B3
B4
Signal driven to the MPC2605
Signal driven by the MPC2605
High–Z
LEGEND
Figure 3. Read Miss Followed by a Burst Read Hit for MPC603/604
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