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參數(shù)資料
| 型號： | MPC2605ZP66R |
| 廠商： | MOTOROLA INC |
| 元件分類： | SRAM |
| 英文描述： | Integrated Secondary Cache for PowerPC Microprocessors |
| 中文描述： | 32K X 72 CACHE TAG SRAM, 8.5 ns, PBGA241 |
| 封裝： | PLASTIC, BGA-241 |
| 文件頁數(shù)： | 21/30頁 |
| 文件大?。?/td> | 288K |
| 代理商： | MPC2605ZP66R |
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MPC2605
21
MOTOROLA
READ/WRITE SNOOP HIT (DIRTY L2 LINE)
Figure 7 is an illustration of a read or write snoop to a
cache line that is dirty in the L2, but is not dirty in the
processor’s cache. When a snoop hits a dirty line, the
MPC2605 will assert ARTRY through the cycle following the
assertion of AACK. This cycle is called the ARTRY window.
Note that the MPC2605 also asserts L2 BR at the same time
it asserts ARTRY. Because the snoop could also have hit a
dirty line in the processor’s cache, the MPC2605 samples
the processor’s BR signal the cycle following the ARTRY
window. This cycle is called the BR window. If the
processor’s BR signal is not asserted, the MPC2605 will start
sampling L2 BG, the cycle after the BR window.
Note that the MPC2605 cannot do a 2–1–1–1 copy back
burst. The earliest that it can handle the first assertion of TA
is two cycles after its assertion of TS.
CLK
CPU BR
L2 BR
L2 BG
TS
A0 – A31
L2 CLAIM
AACK
CPU DBG
L2 DBG
DBB
TA
DH0 – DH31,
DL0 – DL31
CPU BG
A
A
A
ARTRY
A1
A2
A3
A4
1
2
3
4
5
6
7
8
9
10
11
12
Signal driven to the MPC2605
Signal driven by the MPC2605
High–Z
LEGEND
Figure 7. Read or Write Snoop Hit to Dirty L2 Cache Line and Clean Processor Cache Line
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