參數(shù)資料
型號(hào)： MPC2605ZP66R
廠商： MOTOROLA INC
元件分類： SRAM
英文描述： Integrated Secondary Cache for PowerPC Microprocessors
中文描述： 32K X 72 CACHE TAG SRAM, 8.5 ns, PBGA241
封裝： PLASTIC, BGA-241
文件頁(yè)數(shù)： 5/30頁(yè)
文件大?。?/td> 288K
代理商： MPC2605ZP66R
MPC2605
5
MOTOROLA
Pin Locations
Pin Name
Type
Description
2R
TRST
I
Test reset input for IEEE 1149.1 boundary scan (JTAG). If JTAG will not be used,
TRST should be tied low.
3L
TS
I/O
Transfer start I/O from processor bus (can also come from any bus master on the
processor bus). Signals the start of either a processor or bus master cycle.
17F – 19F
*
TSIZ0–TSIZ2
I/O
Transfer size I/O from processor bus.
1K, 2K, 1L, 2L, 1M
*
TT0–TT4
I/O
Transfer type I/O from processor bus.
3H
WT
I/O
Write through status input from processor bus. When tied to ground, the
MPC2605 will operate in write–through mode only (no copy–back).
4C, 15C, 16C, 9D – 11D,
8H – 10H, 4J, 8J, 9J, 16J, 4K,
8K, 12K, 16K, 4L, 11L, 12L,
16L, 10M – 12M, 3T, 9T – 11T,
17T, 3U, 4U, 15U, 17U
VDD
Supply
Power supply: 3.3 V
±
5%.
7C, 9C, 13C, 14C, 7D, 8D,
12D, 13D, 4G, 16G – 18G,
4H, 11H, 12H, 16H, 10J – 12J,
9K – 11K, 8L – 10L, 4M,
8M, 9M, 16M, 4N, 16N, 7T, 8T,
12T, 13T, 5U – 7U, 12U – 14U
VSS
Supply
Ground.
3F, 3R
NC
—
No connection: There is no connection to the chip.
* See pin diagram (page 2) for specific pin assignment of these bus signals.
ABSOLUTE MAXIMUM RATINGS
(See Note 1)
Rating
Symbol
Value
Unit
Power Supply Voltage
VDD
Vin, Vout
Iout
PD
Tbias
TJ
Tstg
– 0.5 to + 4.6
V
Voltage Relative to VSS
Output Current (per I/O)
– 0.5 to VDD + 0.5
±
20
V
mA
Power Dissipation (Note 2)
—
W
Temperature Under Bias
– 10 to + 85
°
C
Operating Temperature
0 to + 125
°
C
Storage Temperature
– 55 to + 125
°
C
NOTES:
1. Permanent device damage may occur if ABSOLUTE MAXIMUM RATINGS are
exceeded. Functional operation should be restricted to RECOMMENDED OPER-
ATING CONDITIONS. Exposure to higher than recommended voltages for extended
periods of time could affect device reliability.
2. Power dissipation capability is dependent upon package characteristics and use
environment. See Package Thermal Characteristics.
This device contains circuitry to protect the
inputs against damage due to high static volt-
ages or electric fields; however, it is advised
that normal precautions be taken to avoid
application of any voltage higher than maxi-
mum rated voltages to this high–impedance
circuit.
This BiCMOS memory circuit has been de-
signed to meet the dc and ac specifications
shown in the tables, after thermal equilibrium
has been established.
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