參數(shù)資料
型號(hào)： MPC2605ZP66R
廠商： MOTOROLA INC
元件分類： SRAM
英文描述： Integrated Secondary Cache for PowerPC Microprocessors
中文描述： 32K X 72 CACHE TAG SRAM, 8.5 ns, PBGA241
封裝： PLASTIC, BGA-241
文件頁(yè)數(shù)： 22/30頁(yè)
文件大?。?/td> 288K
代理商： MPC2605ZP66R
MPC2605
22
MOTOROLA
READ/WRITE SNOOP HIT (DIRTY L2 AND PROCESSOR LINE)
An illustration of PowerPC read or write snoop hit to a dirty
L2 cache line is shown in Figure 8. The processor has a dirty
copy of the cache line. In this case, both the processor and
the MPC2605 assert ARTRY. This situation is detected by
sampling CPU BR in the BR window, as described in the
previous example. If CPU BR is asserted in the BR window,
the MPC2605 will negate L2 BR. It will also ignore assertions
of L2 BG. This allows the processor to write back its dirty
cache line, at which time the MPC2605 will either update or
invalidate its copy depending on whether it is a snoop read or
snoop write.
1
2
3
4
5
6
7
8
9
10
11
12
13
14
A1
A2
A3
A4
A
A
A
CLK
CPU BR
L2 BR
L2 BG
TS
A0 – A31
L2 CLAIM
AACK
CPU DBG
L2 DBG
DBB
TA
DH0 – DH31,
DL0 – DL31
CPU BG
ARTRY
Signal driven to the MPC2605
Signal driven by the MPC2605
High–Z
LEGEND
Figure 8. Read or Write Snoop Hit to Dirty L2 Cache Line and Dirty Processor Cache Line
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