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參數(shù)資料
| 型號： | MPC5606SVLU6R |
| 廠商： | FREESCALE SEMICONDUCTOR INC |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 32-BIT, FLASH, 64 MHz, MICROCONTROLLER, PQFP176 |
| 封裝： | 24 X 24 MM, 1.40 MM HEIGHT, 0.50 MM PITCH, ROHS COMPLIANT, MS-026BGA, LQFP-176 |
| 文件頁數(shù)： | 104/136頁 |
| 文件大?。?/td> | 858K |
| 代理商： | MPC5606SVLU6R |
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MPC5606S Microcontroller Data Sheet, Rev. 7
Freescale Semiconductor
7
It is possible to enable the internal 16 MHz or 128 kHz RC oscillator, the external 4–16 MHz oscillator, or the external
32 KHz oscillator.
It is possible to keep the LCD module active.
The device can be awakened from STANDBY mode via from any of up to 19 I/O pins, a reset or from a periodic wake-up using
a low power oscillator.
STOP mode maintains power to the entire device allowing the retention of all on-chip registers and memory, and providing a
faster recovery low power mode than the lowest STANDBY mode. There is no need to reconfigure the device before executing
code. The clocks to the core and peripherals are halted and can be optionally stopped to the oscillator or PLL at the expense of
a slower start-up time.
STOP is entered from RUN mode only. Wake-up from STOP mode is triggered by an external event or by the internal periodic
wake-up, if enabled.
RUN modes are the main operating mode where the entire device can be powered and clocked and from which most processing
activity is done. Four dynamic RUN modes are supported—RUN0 - RUN3. The ability to configure and select different RUN
modes enables different clocks and power configurations to be supported with respect to each other and to allow switching
between different operating conditions. The necessary peripherals, clock sources, clock speed and system clock prescalers can
be independently configured for each of the four RUN modes of the device.
HALT mode is a reduced activity, low power mode intended for moderate periods of lower processing activity. In this mode the
core system clocks are stopped but user-selected peripheral tasks can continue to run. It can be configured to provide more
efficient power management features (switch-off PLL, flash memory, main regulator, etc.) at the cost of longer wake up latency.
The system returns to RUN mode as soon as an event or interrupt is pending.
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