參數(shù)資料
型號： MPC5606SVLU6R
廠商： FREESCALE SEMICONDUCTOR INC
元件分類： 微控制器/微處理器
英文描述： 32-BIT, FLASH, 64 MHz, MICROCONTROLLER, PQFP176
封裝： 24 X 24 MM, 1.40 MM HEIGHT, 0.50 MM PITCH, ROHS COMPLIANT, MS-026BGA, LQFP-176
文件頁數(shù)： 43/136頁
文件大?。?/td> 858K
代理商： MPC5606SVLU6R
MPC5606S Microcontroller Data Sheet, Rev. 7
Freescale Semiconductor
14
1.6.12
Memory Protection Unit (MPU)
The MPU features the following:
12 region descriptors for per master protection
Start and end address defined with 32-byte granularity
Overlapping regions supported
Protection attributes can optionally include process ID
Protection offered for 3 concurrent read ports
Read and write attributes for all masters
Execute and supervisor/user mode attributes for processor masters
1.6.13
Boot Assist Module (BAM)
The BAM is a block of read-only memory that is programmed once by Freescale. The BAM program is executed every time
the MCU is powered-on or reset in normal mode. The BAM supports different modes of booting. They are:
Booting from internal flash memory
Serial boot loading (A program is downloaded into RAM via FlexCAN or LINFlex and then executed)
Booting from external memory
Additionally the BAM:
Enables and manages the transition of the MCU from reset to user code execution
Configures device for serial bootload
Enables multiple bootcode starting locations out of reset through implementation of search for valid Reset
Configuration Halfword
Enables or disables software watchdog timer out of reset through BAM read of Reset Configuration Halfword option
bit
1.6.14
Enhanced Modular Input/Output System (eMIOS)
MPC5606S microcontrollers have two eMIOS modules—one with 16 channels and one with 8—with input/output channels
supporting a range of 16-bit input capture, output compare, and Pulse Width Modulation functions.
The modules are configurable and can implement 8-channel, 16-bit input capture/output compare or 16-channel, 16-bit output
pulse width modulation/input compare/output compare. Up to five additional channels are configurable as modulus counters.
eMIOS other features include:
Selectable clock source from main FMPLL, auxiliary FMPLL, external 4–16 MHz oscillator or 16 MHz Internal RC
oscillator
Timed I/O channels with 16-bit counter resolution
Buffered updates
Support for shifted PWM outputs to minimize occurrence of concurrent edges
Edge aligned output pulse width modulation
— Programmable pulse period and duty cycle
— Supports 0% and 100% duty cycle
— Shared or independent time bases
Programmable phase shift between channels
Selectable combination of pairs of eMIOS outputs to support sound generation
DMA transfer support
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