MPC5606S Microcontroller Data Sheet, Rev. 7
Freescale Semiconductor
13
All peripheral pins can be alternatively configured as both general purpose input or output pins except ADC channels
which support alternative configuration as general purpose inputs
Direct readback of the pin value supported on all digital output pins through the SIU
Configurable digital input filter that can be applied to up to 14 general purpose input pins for noise elimination on
external interrupts
Register configuration protected against change with soft lock for temporary guard or hard lock to prevent
modification until next reset.
1.6.9
Flash memory
The MPC5606S microcontroller has the following flash memory features:
Up to 1 MB of burst flash memory
— Typical flash memory access time: 0 wait-state for buffer hits, 2 wait-states for page buffer miss at 64 MHz
—Two 4
128-bit page buffers with programmable prefetch control
–
1 set of page buffers can be allocated for code-only, fixed partitions of code and data, all available for any
access
–
1 set of page buffers allocated to Display Controller Unit and the eDMA
— 64-bit ECC with single-bit correction, double-bit detection for data integrity
— 64 KB data flash memory — separate 4
16 KB flash block for EEPROM emulation with prefetch buffer and
128-bit data access port
Small block flash memory arrangement to support features such as boot block, operating system block
Hardware managed flash memory writes, erase and verify sequence
Censorship protection scheme to prevent flash memory content visibility
Separate dedicated 64 KB data flash memory for EEPROM emulation
— 4 erase sectors each containing 16 KB of memory
— Offers Read-While-Write functionality from main program space
— Same data retention and program erase specification as main program flash memory array
1.6.10
SRAM
The MPC5606S microcontrollers have up to 48 KB general-purpose on-chip SRAM with the following features:
Typical SRAM access time: 0 wait-state for reads and 32-bit writes; 1 wait-state for 8- and 16-bit writes if back to back
with a read to same memory block
32-bit ECC with single-bit correction, double bit detection for data integrity
Supports byte (8-bit), half word (16-bit), and word (32-bit) writes for optimal use of memory
User transparent ECC encoding and decoding for byte, half word, and word accesses
Separate internal power domain applied to full SRAM block, 8 KB SRAM block during STANDBY modes to retain
contents during low power mode.
1.6.11
On-chip graphics SRAM
The MPC5606S microcontroller has 160 KB on-chip graphics SRAM with the following features:
Usable as general purpose SRAM
Typical SRAM access time: 0 wait-state for reads and 32-bit writes
Supports byte (8-bit), half word (16-bit), and word (32-bit) writes for optimal use of memory