參數(shù)資料
型號(hào)： MPC5606SVLU6R
廠商： FREESCALE SEMICONDUCTOR INC
元件分類： 微控制器/微處理器
英文描述： 32-BIT, FLASH, 64 MHz, MICROCONTROLLER, PQFP176
封裝： 24 X 24 MM, 1.40 MM HEIGHT, 0.50 MM PITCH, ROHS COMPLIANT, MS-026BGA, LQFP-176
文件頁數(shù)： 99/136頁
文件大?。?/td> 858K
代理商： MPC5606SVLU6R
MPC5606S Microcontroller Data Sheet, Rev. 7
Freescale Semiconductor
65
3.6.4.2
Static latch-up (LU)
Two complementary static tests are required on six parts to assess the latch-up performance:
A supply overvoltage is applied to each power supply pin.
A current injection is applied to each input, output and configurable I/O pin.
These tests are compliant with the EIA/JESD 78 IC latch-up standard.
3.7
Power management electrical characteristics
3.7.1
Voltage regulator electrical characteristics
The internal high power or main regulator (HPREG) requires an external NPN ballast transistor (see Table 21 and Table 22) to
be connected as shown in Figure 7 as well as an external capacitance (CREG) to be connected to the device in order to provide
a stable low voltage digital supply to the device. Capacitances should be placed on the board as near as possible to the associated
pins. Care should also be taken to limit the serial inductance of the board to less than 15 nH.
For the MPC5606S microcontroller, 100 nF should be placed between each of the VDD12/VSS12 supply pairs and also between
the VDDPLL/VSSPLL pair. These decoupling capacitors are in addition to the required stability capacitance. Additionally, 10 F
should be placed between the VDDR pin and the adjacent VSS pin.
VDDR = 3.0 V to 3.6 V / 4.5 V to 5.5 V, TA = 40 to 105 °C, unless otherwise specified.
Table 19. ESD absolute maximum ratings1 2
1 All ESD testing is in conformity with CDF-AEC-Q100 Stress Test Qualification for Automotive Grade Integrated
Circuits.
2 A device will be defined as a failure if after exposure to ESD pulses the device no longer meets the device
specification requirements. Complete DC parametric and functional testing shall be performed per applicable
device specification at room temperature followed by hot temperature, unless specified otherwise in the device
specification.
Symbol
C
Ratings
Conditions
Class
Max value
Unit
VESD(HBM) CC T Electrostatic discharge voltage
(Human Body Model)
TA = 25 °C
conforming to AEC-Q100-002
H1C
2000
V
VESD(MM) CC T Electrostatic discharge voltage
(Machine Model)
TA = 25 °C
conforming to AEC-Q100-003
M2
200
VESD(CDM) CC T Electrostatic discharge voltage
(Charged Device Model)
TA = 25 °C
conforming to AEC-Q100-011
C3A
500
750 (corners)
Table 20. Latch-up results
Symbol
C
Parameter
Conditions
Class
LU
CC
T Static latch-up class
TA = 105 °C
conforming to JESD 78
II level A
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