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參數(shù)資料
| 型號(hào)： | MPC5606SVLU6R |
| 廠商： | FREESCALE SEMICONDUCTOR INC |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 32-BIT, FLASH, 64 MHz, MICROCONTROLLER, PQFP176 |
| 封裝： | 24 X 24 MM, 1.40 MM HEIGHT, 0.50 MM PITCH, ROHS COMPLIANT, MS-026BGA, LQFP-176 |
| 文件頁數(shù)： | 24/136頁 |
| 文件大?。?/td> | 858K |
| 代理商： | MPC5606SVLU6R |
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MPC5606S Microcontroller Data Sheet, Rev. 7
Freescale Semiconductor
12
1.6.6
Interrupt Controller (INTC)
The INTC provides priority-based preemptive scheduling of interrupt requests, suitable for statically scheduled hard real-time
systems.
For high priority interrupt requests, the time from the assertion of the interrupt request from the peripheral to when the processor
is executing the interrupt service routine (ISR) has been minimized. The INTC provides a unique vector for each interrupt
request source for quick determination of which ISR needs to be executed. It also provides an ample number of priorities so that
lower priority ISRs do not delay the execution of higher priority ISRs. To allow the appropriate priorities for each source of
interrupt request, the priority of each interrupt request is software configurable.
When multiple tasks share a resource, coherent accesses to that resource need to be supported. The INTC supports the priority
ceiling protocol for coherent accesses. By providing a modifiable priority mask, the priority can be raised temporarily so that
all tasks which share the resource can not preempt each other.
Multiple processors can assert interrupt requests to each other through software setable interrupt requests. These same software
setable interrupt requests also can be used to break the work involved in servicing an interrupt request into a high priority portion
and a low priority portion. The high priority portion is initiated by a peripheral interrupt request, but then the ISR asserts a
software setable interrupt request to finish the servicing in a lower priority ISR. Therefore these software setable interrupt
requests can be used instead of the peripheral ISR scheduling a task through the RTOS. The INTC provides the following
features:
Unique 9-bit vector for each of the possible 128 separate interrupt sources
8 software triggerable interrupt sources
16 priority levels with fixed hardware arbitration within priority levels for each interrupt source
Ability to modify the ISR or task priority.
— Modifying the priority can be used to implement the Priority Ceiling Protocol for accessing shared resources.
External non maskable interrupt directly accessing the main core critical interrupt mechanism
32 external interrupts
1.6.7
QuadSPI serial flash controller
The QuadSPI module enables use of external serial flash memories supporting single, dual and quad modes of operation. It
features the following:
Memory mapping of external serial flash
Automatic serial flash read command generation by CPU, DMA or DCU read access on AHB bus
Supports single, dual and quad serial flash read commands
Flexible buffering scheme to maximize read bandwidth of serial flash
‘Legacy’ mode allowing QuadSPI to be used as a standard DSPI (no DSI or CSI mode)
1.6.8
System Integration Unit (SIU)
The SIU controls MCU reset configuration, pad configuration, external interrupt, general purpose I/O (GPIO), internal
peripheral multiplexing, and the system reset operation.
The GPIO features the following:
Up to 4 levels of internal pin multiplexing, allowing exceptional flexibility in the allocation of device functions for
each package
Centralized general purpose input output (GPIO) control of up to 132 input/output pins (package dependent)
All GPIO pins can be independently configured to support pull-up, pull down, or no pull
Reading and writing to GPIO supported both as individual pins and 16-bit wide ports
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