參數(shù)資料
型號(hào): MPC755BRX300LE
廠商: MOTOROLA INC
元件分類(lèi): 微控制器/微處理器
英文描述: RISC Microprocessor Hardware Specifications
中文描述: 32-BIT, 300 MHz, RISC PROCESSOR, CBGA360
封裝: 25 X 25 MM, CERAMIC, BGA-360
文件頁(yè)數(shù): 22/56頁(yè)
文件大?。?/td> 1652K
代理商: MPC755BRX300LE
MPC755 RISC Microprocessor Hardware Specifications, Rev. 6.1
22
Freescale Semiconductor
Electrical and Thermal Characteristics
Figure 11
provides the AC test load for TDO and the boundary-scan outputs of the MPC755.
Figure 11. AC Test Load for the JTAG Interface
Figure 12
provides the JTAG clock input timing diagram.
Figure 12. JTAG Clock Input Timing Diagram
TRST assert time
t
TRST
25
ns
2
Input setup times:Boundary-scan data
TMS, TDI
t
DVJH
t
IVJH
4
0
ns
3
Input hold times:Boundary-scan data
TMS, TDI
t
DXJH
t
IXJH
15
12
ns
3
Valid times:Boundary-scan data
TDO
t
JLDV
t
JLOV
4
4
ns
4
Output hold times:Boundary-scan data
TDO
t
JLDH
t
JLOH
25
12
ns
4
TCK to output high impedance:Boundary-scan data
TDO
t
JLDZ
t
JLOZ
3
3
19
9
ns
4, 5
Notes:
1. All outputs are measured from the midpoint voltage of the falling/rising edge of TCLK to the midpoint of the signal in question. The output
timings are measured at the pins. All output timings assume a purely resistive 50-
load (see
Figure 11
). Time-of-flight delays must be added
for trace lengths, vias, and connectors in the system.
2. TRST is an asynchronous level sensitive signal which must be asserted for this minimum time to be recognized.
3. Non-JTAG signal input timing with respect to TCK.
4. Non-JTAG signal output timing with respect to TCK.
5. Guaranteed by design and characterization.
Table 13. JTAG AC Timing Specifications (Independent of SYSCLK)
1
(continued)
At recommended operating conditions (see
Table 3
)
Parameter
Symbol
Min
Max
Unit
Notes
Output
Z
0
= 50
OV
DD
/2
R
L
= 50
TCLK
VM
VM
VM
VM = Midpoint Voltage (OV
DD
/2)
t
TCLK
t
JR
t
JF
t
JHJL
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