參數(shù)資料
型號(hào)： MPC755BRX300LE
廠商： MOTOROLA INC
元件分類： 微控制器/微處理器
英文描述： RISC Microprocessor Hardware Specifications
中文描述： 32-BIT, 300 MHz, RISC PROCESSOR, CBGA360
封裝： 25 X 25 MM, CERAMIC, BGA-360
文件頁(yè)數(shù)： 38/56頁(yè)
文件大?。?/td> 1652K
代理商： MPC755BRX300LE
MPC755 RISC Microprocessor Hardware Specifications, Rev. 6.1
38
Freescale Semiconductor
System Design Information
The MPC755 generates the clock for the external L2 synchronous data SRAMs by dividing the core clock frequency
of the MPC755. The divided-down clock is then phase-adjusted by an on-chip delay-lock-loop (DLL) circuit and
should be routed from the MPC755 to the external RAMs. A separate clock output, L2SYNC_OUT is sent out half
the distance to the SRAMs and then returned as an input to the DLL on pin L2SYNC_IN so that the rising-edge of
the clock as seen at the external RAMs can be aligned to the clocking of the internal latches in the L2 bus interface.
The core-to-L2 frequency divisor for the L2 PLL is selected through the L2CLK bits of the L2CR register. Generally,
the divisor must be chosen according to the frequency supported by the external RAMs, the frequency of the
MPC755 core, and the phase adjustment range that the L2 DLL supports.
Table 17
shows various example L2 clock
frequencies that can be obtained for a given set of core frequencies. The minimum L2 frequency target is 80 MHz.
8.2
PLL Power Supply Filtering
The AV
DD
and L2AV
DD
power signals are provided on the MPC755 to provide power to the clock generation PLL
and L2 cache DLL, respectively. To ensure stability of the internal clock, the power supplied to the AV
DD
input
signal should be filtered of any noise in the 500 kHz to 10 MHz resonant frequency range of the PLL. A circuit
similar to the one shown in
Figure 21
using surface mount capacitors with minimum Effective Series Inductance
(ESL) is recommended. Consistent with the recommendations of Dr. Howard Johnson in
High Speed Digital
Design: A Handbook of Black Magic
(Prentice Hall, 1993), multiple small capacitors of equal value are
recommended over a single large value capacitor.
The circuit should be placed as close as possible to the AV
DD
pin to minimize noise coupled from nearby circuits.
An identical but separate circuit should be placed as close as possible to the L2AV
DD
pin. It is often possible to route
directly from the capacitors to the AV
DD
pin, which is on the periphery of the 360 BGA footprint, without the
inductance of vias. The L2AV
DD
pin may be more difficult to route, but is proportionately less critical.
Table 17. Sample Core-to-L2 Frequencies
Core Frequency (MHz)
÷1
÷1.5
÷2
÷2.5
÷3
250
250
166
125
100
83
266
266
177
133
106
89
275
275
183
138
110
92
300
300
200
150
120
100
325
325
217
163
130
108
333
333
222
167
133
111
350
350
233
175
140
117
366
366
244
183
146
122
375
375
250
188
150
125
400
400
266
200
160
133
Note:
The core and L2 frequencies are for reference only. Some examples may represent core or L2
frequencies which are not useful, not supported, or not tested for by the MPC755; see
Section 4.2.3, “L2
Clock AC Specifications
,” for valid L2CLK frequencies. The L2CR[L2SL] bit should be set for L2CLK
frequencies less than 110 MHz.
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MPC755BRX350TE 功能描述:微處理器 - MPU 360CBGA,RV2.8,HIP4DP RoHS:否 制造商:Atmel 處理器系列:SAMA5D31 核心:ARM Cortex A5 數(shù)據(jù)總線寬度:32 bit 最大時(shí)鐘頻率:536 MHz 程序存儲(chǔ)器大小:32 KB 數(shù)據(jù) RAM 大小:128 KB 接口類型:CAN, Ethernet, LIN, SPI,TWI, UART, USB 工作電源電壓:1.8 V to 3.3 V 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FBGA-324
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MPC755BVT350LE 功能描述:微處理器 - MPU RV2.8,106C RoHS:否 制造商:Atmel 處理器系列:SAMA5D31 核心:ARM Cortex A5 數(shù)據(jù)總線寬度:32 bit 最大時(shí)鐘頻率:536 MHz 程序存儲(chǔ)器大小:32 KB 數(shù)據(jù) RAM 大小:128 KB 接口類型:CAN, Ethernet, LIN, SPI,TWI, UART, USB 工作電源電壓:1.8 V to 3.3 V 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FBGA-324
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