227
ATmega16M1/32M1/64M1 [DATASHEET]
8209E–AVR–11/2012
The values described in
Table 21-3 are typical values. However, due to process variation the temperature sensor
output voltage varies from one chip to another. To be capable of achieving more accurate results the temperature
measurement can be calibrated in the application software. The sofware calibration can be done using the formula:
T = k × [(ADCH << 8) | ADCL] + T
OS
where ADCH and ADCL are the ADC data registers, T is temperature in Kelvin, k is the fixed slope coefficient and
T
OS is the temperature sensor offset. Typically, k is very close to 1.0 and in single-point calibration the coefficient
may be omitted. Where higher accuracy is required the slope coefficient should be evaluated based on measure-
ments at two temperatures.
21.8.1
User calibration
The software calibration requires that a calibration value is measured and stored in a register or EEPROM for each
chip. The software calibration can be done utilizing the formula:
T = {[(ADCH << 8) | ADCL] - T
OS}/k
where ADCH & ADCL are the ADC data registers, k is a fixed coefficient and T
OS is the temperature sensor offset
value determined and stored into EEPROM.
21.8.2
Manufacturing calibration
The calibration values are determined from values measured during test at hot temperature which is approximately
+85°C.
The temperature in Celsius degrees can be calculated utilizing the formula:
T = {[(ADCH << 8) | ADCL] × TSGAIN} + TSOFFSET - 273
Where:
a.
ADCH & ADCL are the ADC data registers.
b.
TSGAIN is the temperature sensor gain (constant 1, or unsigned fixed point number, 0x80 = decimal
1.0).
c.
TSOFFSET is the temperature sensor offset correction term (2. complement signed byte).
21.9
Amplifier
The Atmel ATmega16M1/32M1/64M1 features three differential amplified channels with programmable 5, 10, 20,
and 40 gain stage.
Because the amplifiers are switching capacitor amplifiers, they need to be clocked by a synchronization signal
called in this document the amplifier synchronization clock. To ensure an accurate result, the amplifier input needs
to have a quite stable input value during at least four Amplifier synchronization clock periods.
To ensure an accurate result, the amplifier input needs to have a quite stable input value at the sampling point dur-
ing at least four amplifier synchronization clock periods.
clock CK
ADC equal to eighth the ADC clock frequency. In case the synchronization is done the ADC clock divided
by 8, this synchronization is done automatically by the ADC interface in such a way that the sample-and-hold
occurs at a specific phase of CK
ADC2. A conversion initiated by the user (that is, all single conversions, and the first
free running conversion) when CK
ADC2 is low will take the same amount of time as a single ended conversion (13
ADC clock cycles from the next prescaled clock cycle). A conversion initiated by the user when CK
ADC2 is high will
take 14 ADC clock cycles due to the synchronization mechanism.