180
ATmega16M1/32M1/64M1 [DATASHEET]
8209E–AVR–11/2012
Bit 7– Res: Reserved
This bit is reserved for future use. For compatibility with future devices, it must be written to zero when CANBT2 is
written.
Bit 6:5 – SJW[1:0]: Re-Synchronization Jump Width
To compensate for phase shifts between clock oscillators of different bus controllers, the controller must re-syn-
chronize on any relevant signal edge of the current transmission.
The synchronization jump width defines the maximum number of clock cycles. A bit period may be shortened or
lengthened by a re-synchronization.
Bit 4 – Res: Reserved
This bit is reserved for future use. For compatibility with future devices, it must be written to zero when CANBT2 is
written.
Bit 3:1 – PRS[2:0]: Propagation Time Segment
This part of the bit time is used to compensate for the physical delay times within the network. It is twice the sum of
the signal propagation time on the bus line, the input comparator delay and the output driver delay.
Bit 0 – Res: Reserved
This bit is reserved for future use. For compatibility with future devices, it must be written to zero when CANBT2 is
written.
19.10.10 CANBT3 – CAN Bit Timing Register 3
Bit 7– Res: Reserved
This bit is reserved for future use. For compatibility with future devices, it must be written to zero when CANBT3 is
written.
Bit 6:4 – PHS2[2:0]: Phase Segment 2
This phase is used to compensate for phase edge errors. This segment may be shortened by the re-synchroniza-
tion jump width. PHS2[2:0] shall be
Bit 3:1 – PHS1[2:0]: Phase Segment 1
This phase is used to compensate for phase edge errors. This segment may be lengthened by the re-synchroniza-
tion jump width.
Tsjw = Tscl × (SJW [1:0] + 1)
Tprs = Tscl × (PRS [2:0] + 1)
Bit
765
43210
-
PHS22
PHS21
PHS20
PHS12
PHS11
PHS10
SMP
CANBT3
Read/write
-
R/W
Initial value
-
00
00000
Tphs2 = Tscl × (PHS2 [2:0] + 1)
Tphs1 = Tscl × (PHS1 [2:0] + 1)