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ATmega16M1/32M1/64M1 [DATASHEET]
8209E–AVR–11/2012
17.15 Interrupts
This section describes the specifics of the interrupt handling as performed in Atmel ATmega16M1/32M1/64M1.
17.15.1
Interrupt vector
PSC provides two interrupt vectors:
PSC_End (End of Cycle): When enabled and when a match with POCR_RB occurs
PSC_Fault (Fault Event): When enabled and when a PSC input detects a Fault event
17.15.2
PSC interrupt vectors in ATmega16M1/32M1/64M1
17.16 Register description
Registers are explained for PSC module 0. They are identical for module 1 and module 2.
17.16.1
POC – PSC Output Configuration
Bit 7:6 – Res: Reserved
These bits are reserved and will always read as zero.
Bit 5 – POEN2B: PSC Output 2B Enable
When this bit is clear, I/O pin affected to PSCOUT2B acts as a standard port.
When this bit is set, I/O pin affected to PSCOUT2B is connected to the PSC module 2 waveform generator B out-
put and is set and clear according to the PSC operation.
Bit 4 – POEN2A: PSC Output 2A Enable
When this bit is clear, I/O pin affected to PSCOUT2A acts as a standard port.
When this bit is set, I/O pin affected to PSCOUT2A is connected to the PSC module 2 waveform generator A out-
put and is set and clear according to the PSC operation.
Bit 3 – POEN1B: PSC Output 1B Enable
When this bit is clear, I/O pin affected to PSCOUT1B acts as a standard port.
When this bit is set, I/O pin affected to PSCOUT1B is connected to the PSC module 1 waveform generator B out-
put and is set and clear according to the PSC operation.
Table 17-7.
PSC interrupt vectors.
Vector
no.
Program
address
Source
Interrupt definition
--
-
5
0x0004
PSC_Fault
PSC fault event
6
0x0005
PSC_End
PSC end of Cycle
--
-
--
-
Bit
7
654
3
2
1
0
-
POEN2B
POEN2A
POEN1B
POEN1A
POEN0B
POEN0A
POC
Read/write
R/W
Initial value
0