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ATmega16M1/32M1/64M1 [DATASHEET]
8209E–AVR–11/2012
21.10.10 AMP2CSR – Amplifier 2 Control and Status register
Bit 7 – AMP2EN: Amplifier 2 Enable Bit
Set this bit to enable the Amplifier 2.
Clear this bit to disable the Amplifier 2.
Clearing this bit while a conversion is running will take effect at the end of the conversion.
Warning: Always clear AMP2TS0:1 when clearing AMP2EN.
Bit 6 – AMP2IS: Amplifier 2 Input Shunt
Set this bit to short-circuit the Amplifier 2 input.
Clear this bit to normally use the Amplifier 2.
Bit 5:4 – AMP2G[1:0]: Amplifier 2 Gain Selection Bits
These two bits determine the gain of the Amplifier 2.
To ensure an accurate result, after the gain value has been changed, the amplifier input needs to have a quite sta-
ble input value during at least four Amplifier synchronization clock periods.
Bit 3 – AMPCMP2: Amplifier 2 - Comparator 2 connection
Set this bit to connect the Amplifier 2 to the Comparator 2 positive input. In this configuration the comparator clock
is adapted to the amplifier clock and AMP2TS2, AMP2TS1, AMP2TS0 bits have no effect.
Clear this bit to normally use the Amplifier 2.
Bit 2:0 – AMP2TS[2:0]: Amplifier 2 Clock Source Selection Bits
In accordance with the
Table 21-13, these three bits select the event which will generate the clock for the Amplifier
1. This clock source is necessary to start the conversion on the amplified channel.
101
PSC Module 0 synchronization signal (PSS0)
110
PSC Module 1 synchronization signal (PSS1)
111
PSC Module 2 synchronization signal (PSS2)
Table 21-11. AMP1 clock source selection (Continued).
AMP1TS[2:0]
Clock source
Bit
7
654
3
2
1
0
AMP2EN
AMP2IS
AMP2G1
AMP2G0
AMPCMP2
AMP2TS2
AMP2TS1
AMP2TS0
AMP2CSR
Read/write
R/W
Initial value
0
Table 21-12. Amplifier 2 gain selection.
AMP2G[1:0]
Description
00
Gain 5
01
Gain 10
10
Gain 20
11
Gain 40