144
ATmega16M1/32M1/64M1 [DATASHEET]
8209E–AVR–11/2012
Bit 4:2 – Res: Reserved
These bits are reserved and will always read as zero.
Bit 1 – PCCYC: PSC Complete Cycle
When this bit is set, the PSC completes the entire waveform cycle before halt operation requested by clearing
PRUN.
Bit 0 – PRUN: PSC Run
Writing this bit to one starts the PSC.
17.16.9
PMICn – PSC Module n Input Control Register
The Input Control Registers are used to configure the two PSC’s Retrigger/Fault block A & B. The two blocks are
identical, so they are configured on the same way.
Bit 7 – POVENn: PSC Module n Overlap Enable
Bit 6 – PISELn: PSC Module n Input Select
Clear this bit to select PSCINn as module n input.
Set this bit to select Comparator n output as module n input.
Bit 5 – PELEVn: PSC Module n Input Level Selector
When this bit is clear, the low level of selected input generates the significative event for fault function.
When this bit is set, the high level of selected input generates the significative event for fault function.
Bit 4 – PFLTEn: PSC Module n Input Filter Enable
Setting this bit (to one) activates the Input Noise Canceler. When the noise canceler is activated, the input from the
input pin is filtered. The filter function requires four successive equal valued samples of the input pin for changing
its output. The Input is therefore delayed by four oscillator cycles when the noise canceler is enabled.
Bit 3 – PAOCn: PSC Module n 0 Asynchronous Output Control
Bit 2:0 – PRFMn2:0: PSC Module n Input Mode
These three bits define the mode of operation of the PSC inputs.
Bit
7
654
3
2
1
0
POVENn
PISELn
PELEVn
PFLTEn
PAOCn
PRFMn2
PRFMn1
PRFMn0
PMICn
Read/write
R/W
Initial value
0