參數(shù)資料
型號(hào)： MT90812
廠商： Mitel Networks Corporation
英文描述： Integrated Digital Switch (IDX)(集成數(shù)字開關(guān))
中文描述： 綜合數(shù)字交換機(jī)（IDX的）（集成數(shù)字開關(guān)）
文件頁(yè)數(shù)： 15/105頁(yè)
文件大?。?/td> 334K
代理商： MT90812
Advance Information
MT90812
11
Control Register and the use of Connection Memory
Connect Memory Configurations for Expansion Bus Modes
Each will be described below. A full description of addressing memory in the MT90812 is given in “Address
Memory Map” starting on page 12. Refer to Section 21.0 for a definition of the Connection Memory High and
Low bits.
4.2.1
Locations in the Connection Memory, which is split into high and low parts, are associated with particular TDM
output streams. When a channel is due to be transmitted on an TDM output stream, the data for the channel
can either be switched from an TDM input stream or it can originate from the microprocessor. If the data is
switched from an input, then the contents of the Connection Memory Low location associated with the output
channel is used to address the Data Memory.
Connection Memory Usage for Switch Connection or Message Mode
The Data Memory address corresponds to the channel on the input stream on which the data for switching
arrived. If the data for the output channel originates from the microprocessor (Message Mode), then the
contents of the Connection Memory Low location associated with the output channel are output directly, and
this data is output repetitively on the channel once every frame until the microprocessor intervenes.
The Connection Memory High determines whether individual output channels are in Message Mode, controls
individual output channels to go into a high-impedance state and specifies the gain for each outgoing channel.
4.2.2
If the microport is operating in multiplexed mode, addressing the high and low sections of Connection Memory
is done by setting the Memory Select Bits in Control Register. If the microport is operating in non-multiplexed
mode, addressing the high and low sections of connection memory is done by setting the external address bits
A9,A8,A7. Refer to “Address Memory Select Register (AMS)” on page 53, and “Microprocessor Port” on
page 49.
Connection Memory Select
The Control Register also consists of mode control bits that allows the chip to broadcast messages on all TDM
output channels (i.e., to put every channel into Message Mode). Mode control bit 5, CT2:MSG bit, puts every
output channel on every output stream into active Message Mode; i.e., the contents of the Connection Memory
Low are output on the TDM output streams once every frame unless the ODE pin is low. In this mode the chip
behaves as if bits 2 and 0 of every Connection Memory High location were 1, regardless of the actual values.
If CAR:MSG bit is 0, then bits 2 and 0 of each Connection Memory High location function as follows. If CMH:bit
2 is set to 1, the associated TDM output channel is in Message Mode; i.e., the byte in the corresponding
Connection Memory Low location is transmitted on the stream at that channel. Otherwise, the serial input is
transmitted and the Connection Memory Low defines the associated input stream and channel where the byte
is to be found.
If the ODE pin is low, then all serial outputs are high-impedance. If the ODE pin is high and CAR:MSG bit is 1,
then all outputs are active. If the ODE pin is high and CAR:MSG bit is 0, then the bit 0 in the Connection
Memory High location enables the output driver for the corresponding individual output stream and channel.
CMH:bit 0=1 enables the driver and CMH:bit 0=0 disables it.
4.2.3
In TDM Link mode, the 128 Connect Memory locations reserved for the expansion bus are associated with the
outgoing channels of EST0.
Connect Memory Configurations for Expansion Bus Modes
In IDX Link mode, there are 32 outgoing channels for the EST0 stream. For the EST1 stream there are 96
outgoing channels. In this mode the Connection Memory is configured such that the first 32 locations are used
for the EST0 stream. The next 96 locations are for the EST1 stream as selected by the Expansion Bus Position
bits as described in “Address Memory Map” on page 12.
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