參數(shù)資料
型號(hào)： MT90812
廠商： Mitel Networks Corporation
英文描述： Integrated Digital Switch (IDX)(集成數(shù)字開(kāi)關(guān))
中文描述： 綜合數(shù)字交換機(jī)（IDX的）（集成數(shù)字開(kāi)關(guān)）
文件頁(yè)數(shù)： 60/105頁(yè)
文件大?。?/td> 334K
代理商： MT90812
MT90812
Advance Information
56
22.4
Output Clocking Control Register (OCC)
The register is configured as follows:
22.5
Interrupt Status Register (INTS)
The
INTS
register is configured as follows:
Read/Write Address is: 003
H
Reset Value is: 00
H
Bit
Name
Description
7
PCOS
PLL Clock Output Select
. With PE=1, when PCS = 1 selects clocks generated from the
PLL for use in outgoing EST1/0 TDM streams, F8o and C8o. Otherwise the clocks are
derived directly from the Input Clock Reference. With C4 as the input clock reference,
EST0/1, 4 and 8 Mb/s timing, as well as F8o and C8o, are generated from the PLL
independent of PCOS. Refer to Table 9, “Clock Modes,” on page 25 and Section 9.2.5
6
-
Unused
.
5
C10E
C10 Output Enable
. When 0, C10o is high impedance. When 1 and the PLL is enabled, C10o
is enabled.
4
C8E
C8 Output Enable
. When 0, C8 is high impedance. When 1 and the Input Clock Reference is
not C8, then C8 is enabled.
3
F8E
F8 Output Enable
. When 0, F8 is high impedance. When 1 and the Input Clock Reference is
not C8, then F8 is enabled.
2
C4E
C4 Output Enable
. When 0, C4 is high impedance. When 1, then C4 is enabled.
1
F4E
F4 Output Enable
. When 0, F4 is high impedance. When 1, then F4o is enabled.
0
C2E
C2 Output Enable
. When 0, C2 is high impedance. When 1, then C2 is enabled.
Read Address is: 004
H
Reset Value is: 00
H
Bit
Name
Description
7
DRE
D-Channel Receive FIFO Error
. Status indicated in “D-Channel BR Status
(DRXS)” on page 68.
6
DRX
D-Channel Receiver attained the message length in MLI mode or the RX FIFO
interrupt trigger level (number of words) in FLI mode.
5
DTX
D-Channel Transmit FIFO empty or 3/4 empty or transmission complete.
4
FTS
Memory empty status for the FSK transmit memory or end of transmission.
3
EDBS
Energy Detect Block B interrupt
.
2
EDAS
Energy Detect Block A interrupt
.
7
6
5
4
3
2
1
0
C2E
F4E
C4E
C8E
C10E
-
PCOS
F8E
7
6
5
4
3
2
1
0
EDAS
CFS
C8F
EDBS
FTS
DTX
DRX
DRXE
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