參數(shù)資料
型號(hào)： MT90812
廠商： Mitel Networks Corporation
英文描述： Integrated Digital Switch (IDX)(集成數(shù)字開(kāi)關(guān))
中文描述： 綜合數(shù)字交換機(jī)（IDX的）（集成數(shù)字開(kāi)關(guān)）
文件頁(yè)數(shù)： 27/105頁(yè)
文件大?。?/td> 334K
代理商： MT90812
Advance Information
MT90812
23
Table 6 - Output Channels for Minimum Delay
The output channel number m, specified for minimum delay in these four cases account for there being two
4.096Mb/s channels and four 8.192Mb/s channels for every one 2.048Mb/s channel.
Table 7 lists the condition required for a throughput delay of less than one frame period, the throughput delay if
this condition is met and the throughput delay expressed in timeslots when switching is made in the following
frame. For cases where there are different data rates the delay is expressed in timeslots associated with the
fastest data rate. i.e. with the source channel from Est1 (@8Mb/s) and destination channel on STo1 (@2Mb/s)
the delay is expressed in 8Mb/s timeslots. If the incoming 8Mb/s channel, n = 119, outgoing 2Mb/s channel m
=31, then the delay = 4m-n = 4(31)-119= five 8Mb/s timeslots. If m=1 the delay=128-(n-4m)=128-(119-
4)=thirteen 8Mb/s timeslots.
Table 7 - Throughput Delay for Minimum Delay Mode
Notes: t.s. = time-slot. t.s
. =2Mb/s t.s. = 3.9 us. t.s
. =4Mb/s t.s.=1.95 us. t.s
.=8Mb/s t.s.=0.975 us.
Delays are measured in timeslots and at the point in time from when the input channel is completely shifted in and when the output
channel is completely shifted out.
Source and Destination Streams
Expansion Bus Data Rate
2.048 Mb/s
4.096 Mb/s
8.192 Mb/s
Sti0/1 -> Sto0/1
m>=n+2
N/A
N/A
Est0/1 -> Est0/1
m>=n+2
Sti0/1 -> Est0/1
m>=2n+3
m>=4n+5
Est0/1 -> Sto0/1
m>=(n+3)/2
m>=(n+5)/4
Source and Destination
Streams
Input
channel,
n, range
Output
channel,
m, range
Condition for
switching
within same
frame
Throughput
Delay within
same frame
Throughput
Delay if
condition not
met
Sti0/1 -> Sto0/1
0-31
0-31
m>=n+2
m-n t.s
2
.
m-n t.s
2
.
32-(n-m) t.s
2
.
32-(n-m) t.s
2
.
Est0/1 -> Est0/1 2.048
Mb/s
0-31
0-31
m>=n+2
Est0/1 -> Est0/1 4.096
Mb/s
0-64
0-64
m-n t.s
4
.
64-(n-m) t.s
4
.
Est0/1 -> Est0/1 8.192
Mb/s
0-127
0-127
m-n t.s
8
.
128-(n-m) t.s
8
.
Sti0/1 -> Est0/1 2.048 Mb/
s
0-31
0-31
m>=n+2
m-n t.s
2
.
32-(n-m) t.s
2
.
Sti0/1 -> Est0/1 4.096 Mb/
s
0-31
0-64
m>=2n+3
m-2n t.s
4
.
64-(2n-m) t.s
4
.
Sti0/1 -> Est0/1 8.192 Mb/
s
0-31
0-127
m>=4n+5
m-4n t.s
8
.
128-(4n-m) t.s
8
.
Est0/1 2.048 Mb/s -> Sti0/
1
0-31
0-31
m>=n+2
m-n t.s
2
.
32-(n-m) t.s
2
.
Est0/1 4.096 Mb/s ->
Sti0/1
0-64
0-31
m>=(n+3)/2
2m-n t.s
4
.
64-(n-2m) t.s
4
.
Est0/1 8.192 Mb/s ->
Sti0/1
0-127
0-31
m>=(n+5)/4
4m-n t.s
8
.
128-(n-4m) t.s
8
.
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參數(shù)描述
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