參數(shù)資料
型號(hào)： MT90812
廠商： Mitel Networks Corporation
英文描述： Integrated Digital Switch (IDX)(集成數(shù)字開關(guān))
中文描述： 綜合數(shù)字交換機(jī)（IDX的）（集成數(shù)字開關(guān)）
文件頁數(shù)： 38/105頁
文件大?。?/td> 334K
代理商： MT90812
MT90812
Advance Information
34
12.1
Transmitter Interrupt Handling
In either MLI or FLI modes interrupts are generated on TX FIFO empty or 3/4 empty, or end of transmission.
The TX FIFO Interrupt Select (IS) and Interrupt Level (IL) bits in the DTXC register specify the condition for an
interrupt to occur. If the IS bit is set high, then the interrupt occurs when transmission is complete.
Table 12 - Number of available frames to continue the message following TX FIFO empty interrupt
If the IS bit is zero, then an interrupt occurs when either the TX FIFO is empty or 3/4 empty depending on the
status of the IL bit. This type of interrupt can be used to continue the message. Therefore, to continue a
message after the TX FIFO empty interrupt occurs, the user can write to the TX FIFO within the number of
frames as shown in Table 12.
The D-Channel TX Enable Interrupt (DTXE) bit in the “Interrupt Enable Register (INTE)” on page 57 enables or
disables the Transmitter interrupts.
13.0 HDLC Resource Allocator Module
The HDLC Resource Allocator (HRA) block in the MT90812 provides an interface to the MT8952 HDLC
Protocol Controller. This interface supports the sharing of the HDLC resource across several MT9171/72 DNIC
devices for communication over the D-Channel. The MSAN-122 application note describes how voice/data
channels and signalling information channels on a digital communications link are supported. Refer to the
MSAN-122 note for a general description of:
MT8952 HDLC Protocol Controller
MT9171/72 Digital Network Interface Circuit
Shared HDLC Resource Method
The HRA block is described in the following sections.
General Description of MT90812 and Shared HDLC Configuration
Connection to MT8952 HDLC Controller and MT9171/72 DNIC
Connection to MT8952B HDLC Controller
Connection to MT9171/72 DNIC
Data Stream Flow
TX Control
Generation of TxCEN
End of the Transmission of a Packet
TX and RX Handshaking
Merging of D and C-channels
RX Control
Generation of RxCEN
Mode name
Interrupt Mode
Bit Rate
1 bit/frame
2 bits/frame
8 bits/frame
Message oriented
MLIM
8 frames
4 frames
1 frame
Message oriented with parity
MLIM
8 frames
4 frames
1 frame
Unframed
FLIM
8 frames
4 frames
1 frame
Byte oriented
FLIM
10 frames
5 frames
1 frame
Byte oriented with parity
FLIM
11 frames
6 frames
1 frame
相關(guān)PDF資料
PDF描述
MT90840AK Distributed Hyperchannel Switch
MT90840AP Distributed Hyperchannel Switch
MT9085B PAC - Parallel Access Circuit(并行存取電路)
MT9092 Digital Telephone with HDLC(數(shù)字電話（帶高階數(shù)據(jù)鏈路控制HDLC）)
MT9092 ISO2-CMOS ST-BUS⑩ FAMILY Digital Telephone with HDLC (HPhone-II)
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
MT90812AL 制造商:Microsemi Corporation 功能描述:SWIT FABRIC 192 X 192 16.384MBPS 5V 64MQFP - Trays 制造商:Zarlink Semiconductor Inc 功能描述:SWIT FABRIC 192 X 192 16.384MBPS 5V 64MQFP - Trays
MT90812AL1 制造商:Microsemi Corporation 功能描述:SWIT FABRIC 192 X 192 16.384MBPS 5V 64MQFP - Trays 制造商:Microsemi Corporation 功能描述:PB FREE INTEGRATED DIGITAL SWITCH
MT90812AP 制造商:MITEL 制造商全稱:Mitel Networks Corporation 功能描述:Integrated Digital Switch (IDX)
MT90812AP1 制造商:Zarlink Semiconductor Inc 功能描述:SWIT FABRIC 192 X 192 16.384MBPS 5V 68PLCC /BAKE/DRYPACK - Rail/Tube 制造商:Zarlink Semiconductor Inc 功能描述:INTEGRATED DIGITAL SWCH
MT90812APR 制造商:Microsemi Corporation 功能描述:SWIT FABRIC 192 X 192/64 X 64 1.048GBPS 5V 68PLCC - Tape and Reel
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