參數(shù)資料
型號: MT90812
廠商: Mitel Networks Corporation
英文描述: Integrated Digital Switch (IDX)(集成數(shù)字開關(guān))
中文描述: 綜合數(shù)字交換機(jī)(IDX的)(集成數(shù)字開關(guān))
文件頁數(shù): 94/105頁
文件大小: 334K
代理商: MT90812
MT90812
Advance Information
90
See "Notes" following AC Electrical Characteristics tables.
See "Notes" following AC Electrical Characteristics tables.
AC Electrical Characteristics - Output Delay Parameters Referenced to Input Clock
Signals
Characteristics
Sym
Min
Max
Units
Test Conditions
Output Driver Enable Delay
(2.048, 4.096, 8.192 Mb/s)
t
OED
55
ns
3
STo delay, active to active, High-
Z to active, active to High-Z
2.048 Mb/s
4.096 Mb/s
8.192 Mb/s
t
SToD
,
t
ZD,
t
DZ
65
55
55
ns
ns
ns
Non-PLL Clock
3, 9, 10.
Sto delay, active to active, High-Z
to active, active to High-Z
2.048 Mb/s - Sto0,Sto1
2.048 Mb/s - EST0
4.096 Mb/s
8.192 Mb/s
t
SToD
,
t
ZD,
t
DZ
45
45
45
45
ns
ns
ns
ns
PLL Output Clock
3, 11, 14, 15
3, 11, 14, 16
3, 11, 14, 16
3, 11, 14, 16
Clock Output Delays
C2o
C4ob
C8o
t
c2od
t
c4od
t
c8od
50
50
40
ns
ns
ns
Non-PLL Clock. 3, 9,10
Clock Output Delays
C2o
C4ob
C8o
C10o
t
c2od
t
c4od
t
c8od
t
c10od
35
35
30
35
ns
ns
ns
ns
PLL Output Clock
3, 11, 14, 15
3, 11, 14, 15
3, 11, 14, 16
3, 11, 14
AC Electrical Characteristics - Input Set and Hold Parameters Referenced to Input Clock
Signals
Characteristics
Sym
Min
Max
Units
Test Conditions
Sti Set-up Time
before CLK rising (ST-Bus mode)
before CLK falling (GCI mode)
2.048 Mb/s - Sto0,Sto1,EST1
4.096 Mb/s
8.192 Mb/s
t
STiS
5
5
5
ns
ns
ns
Non-PLL Clock
3, 9, 10
Sti Set-up Time
before CLK rising (ST-Bus mode)
before CLK falling (GCI mode)
2.048 Mb/s - Sto0,Sto1,EST1
4.096 Mb/s
8.192 Mb/s
t
STiS
10
10
5
ns
ns
ns
PLL Clock
3, 11, 14, 15
1, 3, 11, 14, 16
2, 3, 11, 14, 16
Sti Hold Time
before CLK rising (ST-Bus mode)
before CLK falling (GCI mode)
2.048 Mb/s - Sto0,Sto1,EST1
4.096 Mb/s
8.192 Mb/s
t
STiH
20
20
20
ns
ns
ns
Non-PLL Clock. 3, 9, 10
PLL Clock. 3, 11, 14, 15
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