- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄383645 > MT90812 (Mitel Networks Corporation) Integrated Digital Switch (IDX)(集成數(shù)字開關(guān)) PDF資料下載
參數(shù)資料
| 型號： | MT90812 |
| 廠商： | Mitel Networks Corporation |
| 英文描述： | Integrated Digital Switch (IDX)(集成數(shù)字開關(guān)) |
| 中文描述： | 綜合數(shù)字交換機(jī)（IDX的）（集成數(shù)字開關(guān)） |
| 文件頁數(shù)： | 50/105頁 |
| 文件大?。?/td> | 334K |
| 代理商： | MT90812 |
第1頁第2頁第3頁第4頁第5頁第6頁第7頁第8頁第9頁第10頁第11頁第12頁第13頁第14頁第15頁第16頁第17頁第18頁第19頁第20頁第21頁第22頁第23頁第24頁第25頁第26頁第27頁第28頁第29頁第30頁第31頁第32頁第33頁第34頁第35頁第36頁第37頁第38頁第39頁第40頁第41頁第42頁第43頁第44頁第45頁第46頁第47頁第48頁第49頁當(dāng)前第50頁第51頁第52頁第53頁第54頁第55頁第56頁第57頁第58頁第59頁第60頁第61頁第62頁第63頁第64頁第65頁第66頁第67頁第68頁第69頁第70頁第71頁第72頁第73頁第74頁第75頁第76頁第77頁第78頁第79頁第80頁第81頁第82頁第83頁第84頁第85頁第86頁第87頁第88頁第89頁第90頁第91頁第92頁第93頁第94頁第95頁第96頁第97頁第98頁第99頁第100頁第101頁第102頁第103頁第104頁第105頁
MT90812
Advance Information
46
Figure 26 - Data Flow for FSK transmitter
Data is written to the FSK FIFO. Start and Stop bits are added to each byte. The FSK modulator generates two
output frequencies, representing the ‘marks’ and ‘spaces’. At 1200 baud, one bit is transmitted every 6
2
/
3
frames. The resulting PCM encoded signal is written to DM where it can be switched to any outgoing channel.
When an interrupt occurs the FTS bit is set in the Interrupt Status Register (INTS). The interrupt may be
enabled by setting the FTE bit in Interrupt Enable Register (INTE). An FSK interrupt may occur for two reasons.
When the FIS bit, in the Ringer and FSK Control Register (RFC), is Low, an interrupt is generated when the TX
FIFO is empty, when the FIS bit is High, an interrupt is generated at the end of transmission.
The FIFO empty interrupt will occur when the last byte has been read and before the byte has been
transmitted. FSK transmitter will finish transmitting this last byte 11 bits (73 1/3 frames) later and start the idle
state if the FIFO has not been refilled. The 11 bits include the start bit, 8 bits from the FIFO and 2 idle bits.
End of transmission must be confirmed before disabling the FSK transmitter or switching to another output
channel. The end of transmission can be selected by setting the FIS bit. End of transmission interrupt will occur
after 2 idle state bits have been transmitted. Subsequently end of transmission interrupts occur once every 8
idle state bits.
This interrupt can also be used by the system to count the number of bits sent in the channel seizure and mark
preamble before the FSK data. When the FSK transmitter is enabled, by setting the FEN bit in the FSK Control
Register, and the FIFO is not written to, the first end of transmission interrupt is after 2 idle state bits (13 1/3
frames). Subsequent interrupts are once every 8 bits (53 1/3 frames).
In addition to selecting the type of interrupt the Ringer and FSK Control Register (RFC) is used to select the
idle state of continuous ‘mark’ or continuous ‘space’, the ‘mark’ and ‘space’ frequency standard, and to turn on
or off the transmitter. Also, a ‘channel seizure’ signal of alternating ones and zero’s can be enabled. Refer to
the description of the “Ringer and FSK Control Register (RFC)” on page 58.
Programming sequence for on-hook data transmission (channel seizure + mark + data packet):
Transmit Channel seizure
1.
FEN initially 0 so that FSK transmit is disabled. Select end of transmission interrupt and enable.
FSK interrupt. Select channel seizure as idle state.
2.
Enable transmission via FEN=1. Use end of transmission interrupt to count how many bits have
been transmitted. The first interrupt occurs after two idle state bits (13 1/3 frames) have been sent.
FSKM
Data Memory
FSK Transmitter
Uport Write
Connect Memory
Control Registers
Parallel to Serial
Output Stream
Channel m
FSK FIFO
0100 1001
0
PCM byte
1
2
1 - FSK modulator that generates two output frequencies, representing the ‘marks’ and
‘spaces’. Start and Stop bits are added to each byte.
2 - FSK transmitter outputs PCM coded signal.
1
5F
H
07
H
5F
H
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| MT90840AK | Distributed Hyperchannel Switch |
| MT90840AP | Distributed Hyperchannel Switch |
| MT9085B | PAC - Parallel Access Circuit(并行存取電路) |
| MT9092 | Digital Telephone with HDLC(數(shù)字電話（帶高階數(shù)據(jù)鏈路控制HDLC）) |
| MT9092 | ISO2-CMOS ST-BUS⑩ FAMILY Digital Telephone with HDLC (HPhone-II) |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| MT90812AL | 制造商:Microsemi Corporation 功能描述:SWIT FABRIC 192 X 192 16.384MBPS 5V 64MQFP - Trays 制造商:Zarlink Semiconductor Inc 功能描述:SWIT FABRIC 192 X 192 16.384MBPS 5V 64MQFP - Trays |
| MT90812AL1 | 制造商:Microsemi Corporation 功能描述:SWIT FABRIC 192 X 192 16.384MBPS 5V 64MQFP - Trays 制造商:Microsemi Corporation 功能描述:PB FREE INTEGRATED DIGITAL SWITCH |
| MT90812AP | 制造商:MITEL 制造商全稱:Mitel Networks Corporation 功能描述:Integrated Digital Switch (IDX) |
| MT90812AP1 | 制造商:Zarlink Semiconductor Inc 功能描述:SWIT FABRIC 192 X 192 16.384MBPS 5V 68PLCC /BAKE/DRYPACK - Rail/Tube 制造商:Zarlink Semiconductor Inc 功能描述:INTEGRATED DIGITAL SWCH |
| MT90812APR | 制造商:Microsemi Corporation 功能描述:SWIT FABRIC 192 X 192/64 X 64 1.048GBPS 5V 68PLCC - Tape and Reel |
發(fā)布緊急采購，3分鐘左右您將得到回復(fù)。