參數(shù)資料
型號(hào): MT90812
廠(chǎng)商: Mitel Networks Corporation
英文描述: Integrated Digital Switch (IDX)(集成數(shù)字開(kāi)關(guān))
中文描述: 綜合數(shù)字交換機(jī)(IDX的)(集成數(shù)字開(kāi)關(guān))
文件頁(yè)數(shù): 43/105頁(yè)
文件大小: 334K
代理商: MT90812
Advance Information
MT90812
39
13.3.4
The HRA block multiplexes the D-channel, originating at the HDLC Protocol Controller, and the C-channels into
a common output stream. C-channel and D-channel information destined for the line circuit are also fed
through a multiplexer controlled by TxCEN and a half-frame count. This does the merging of the outgoing D-
and C-channel information and produces a high (’all-ones’) pattern on the unused D-channels.
Merging of D and C-channels.
Figure 25 - Composite ST-BUS Frame for HRA Application
Fig. 25 shows the composition of the ST-BUS in the transmit direction. The streams are also labelled according
to the numbers assigned as in Fig. 24.
The B1 and B2 channels for up to 16 line circuits arrive at STi0
stream #3
and depart at STo0
stream #1
. All
DNIC line circuits are connected in parallel to this bus. The channel assignments and line destination
addresses are shown in Fig. 24. The C-channel information, which have been written to the MT90812 Connect
Memory, are assigned to the first 16 channels of STo1,
stream #2
.
The D-channel from the MT8952B is input to the HRA block of the MT90812 at DPER,
stream #5
, during the
times enabled by TxCEN. The C and D-channels are combined to produce STo1,
stream #2
, which is then
routed to the DNICs. The composition of CDSTo is shown, in Fig. 24, with the D-channel enabled for line circuit
3 (channel 18).
In the opposite direction, C-channel information from the line circuits arrives at STi1,
stream #4
, in the first
16 channels. The MT8952B, enabled by RxCEN, receives the active incoming D-channel directly from the
same bus.
14.0 RX Control
14.1
RX Circuit Functions
The RX circuit performs the following functions:
generate RxCEN to enable the HDLC receiver
operate in dedicated mode or multiplexed modes
handle Receive Packet Termination
generate the CTS pattern to be transmitted
0
1
2
3
4
5
6
15
16
17
18
19
20
21
22
23
24
25
31
Channel
F0i
F0o
CSTi
DPER
#5
TxCEN
STo1
#2
STi/o0
#3/#1
C0
C1
C2
C3
C4
C5
C6
C7
C8
C9
C10
C15
D
D
0
D
1
C0
C1
C2
C3
C4
C5
C6
C7
C8
C9
C10
C15
D
B2
B2
B2
B2
B2
B2
B2
B2
B2
B2
B2
B2
B1
B1
B1
B1
B1
B1
B1
B1
1
2
3
4
5
6
7
8
9
10
11
1
2
3
4
5
6
7
16
16
26
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