參數(shù)資料
型號: P60ARM-GP1N
廠商: Zarlink Semiconductor Inc.
英文描述: Low power, general purpose 32-bit RISC microprocessor
中文描述: 低功耗,通用32位RISC微處理器
文件頁數(shù): 102/120頁
文件大?。?/td> 1275K
代理商: P60ARM-GP1N
P60ARM-B
98
Notes:
1.
TCK
may be stopped indefinitely in either the low or high phase.
2.
Assumes a 25pF load on
TDO
. Output timing derates at 0.072ns/pF of extra load applied.
3.
TDO
enable time applies when the TAP controller enters the Shift-DR or Shift-IR states.
4.
TDO
disable time applies when the TAP controller leaves the Shift-DR or Shift-IR states.
5.
For correct data latching, the I/O signals (from the core and the pads) must be setup and held with
respect to the rising edge of
TCK
in the CAPTURE-DR state of the SAMPLE/PRELOAD, INTEST
and EXTEST instructions.
6.
Assumes that the data outputs are loaded with the AC test loads (see AC parameter specification).
7.
Data output enable time applies when the boundary scan logic is used to enable the output drivers.
8.
Data output disable time applies when the boundary scan is used to disable the output drivers.
9.
TMS
must be held high as
nTRST
is taken high at the end of the boundary-scan reset sequence.
Symbol
Parameter
Min
Typ
Max
Units
Notes
Tbscl
TCK
low period
48
ns
1
Tbsch
TCK
high p
eriod
48
ns
1
Tbsis
TDI
,
TMS
setup to [TCr]
10
ns
Tbsih
TDI
,
TMS
hold from [TCr]
10
ns
Tbsod
TCf to
TDO
valid
40
ns
2
Tbsoh
TDO
hold time
3
ns
2
Tbsoe
TDO
enable time
5
ns
2,3
Tbsoz
TDO
disable time
40
ns
2,4
Tbsss
I/O signal setup to [TCr]
10
ns
5
Tbssh
I/O signal hold from [TCr]
15
ns
5
Tbsdd
TCf to data output valid
30
ns
Tbsdh
data output hold time
3
ns
6
Tbsde
data output enable time
5
ns
6,7
Tbsdz
data output disable time
20
ns
6,8
Tbsr
Reset period
20
ns
Tbsrs
tms setup to [TRr]
10
ns
9
Tbsrh
tms hold from [TRr]
10
ns
9
Table 24: ARM60 Boundary Scan Interface Timing
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