參數(shù)資料
型號: P60ARM-GP1N
廠商: Zarlink Semiconductor Inc.
英文描述: Low power, general purpose 32-bit RISC microprocessor
中文描述: 低功耗,通用32位RISC微處理器
文件頁數(shù): 24/120頁
文件大?。?/td> 1275K
代理商: P60ARM-GP1N
P60ARM-B
20
4.2 The Condition Field
Figure 6: Condition Codes
All ARM60 instructions are conditionally executed, which means that their execution may or may not take
place depending on the values of the N, Z, C and V flags in the CPSR. The condition encoding is shown in
Figure 6: Condition Codes
.
If the
(NV) class of condition codes shall not be used as they will be redefined in future variants of the ARM
architecture. If a NOP is required it is suggested that MOV R0,R0 be used. The assembler treats the absence
of a condition code as though
always
had been specified.
always
(AL) condition is specified, the instruction will be executed irrespective of the flags. The
never
The other condition codes have meanings as detailed in
(EQual) causes the instruction to be executed only if the Z flag is set. This would correspond to the case
where a compare (CMP) instruction had found the two operands to be equal. If the two operands were
different, the compare instruction would have cleared the Z flag and the instruction will not be executed.
Figure 6: Condition Codes
, for instance code 0000
Cond
31
28 27
0
Condition field
0000 = EQ - Z set (equal)
0001 = NE - Z clear (not equal)
0010 = CS - C set (unsigned higher or same)
0011 = CC - C clear (unsigned lower)
0100 = MI - N set (negative)
0101 = PL - N clear (positive or zero)
0110 = VS - V set (overflow)
0111 = VC - V clear (no overflow)
1000 = HI - C set and Z clear (unsigned higher)
1001 = LS - C clear or Z set (unsigned lower or same)
1010 = GE - N set and V set, or N clear and V clear (greater or equal)
1011 = LT - N set and V clear, or N clear and V set (less than)
1100 = GT - Z clear, and either N set and V set, or N clear and V clear (greater than)
1101 = LE - Z set, or N set and V clear, or N clear and V set (less than or equal)
1110 = AL - always
1111 = NV - never
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