參數(shù)資料
型號: P60ARM-GP1N
廠商: Zarlink Semiconductor Inc.
英文描述: Low power, general purpose 32-bit RISC microprocessor
中文描述: 低功耗,通用32位RISC微處理器
文件頁數(shù): 97/120頁
文件大?。?/td> 1275K
代理商: P60ARM-GP1N
Boundary Scan Test Interface
93
8.5.7 IDCODE (1110)
The IDCODE instruction connects the device identification register (or ID register) between
TDI
and
TDO
.
The ID register is a 32-bit register that allows the manufacturer, part number and version of a component
to be determined through the TAP.
When the instruction register is loaded with the IDCODE instruction, all the boundary-scan cells are placed
in their normal (system) mode of operation.
In the CAPTURE-DR state, the device identification code (specified at the end of this section) is captured
by the ID register. In the SHIFT-DR state, the previously captured device identification code is shifted out
of the ID register via the
TDO
pin, whilst data is shifted in via the
TDI
pin into the ID register. In the
UPDATE-DR state, the ID register is unaffected.
The device identification codes for the P60ARM (obsolete) and P60ARM-B are as follows:
P60ARM
P60ARM-B
1
3
D4A7
CCA
06F
06F
8.5.8 BYPASS (1111)
The BYPASS instruction connects a 1 bit shift register (the BYPASS register) between
TDI
and
TDO
.
When the BYPASS instruction is loaded into the instruction register, all the boundary-scan cells are placed
in their normal (system) mode of operation. This instruction has no effect on the system pins.
In the CAPTURE-DR state, a logic 0 is captured by the bypass register. In the SHIFT-DR state, test data is
shifted into the bypass register via
TDI
and out via
TDO
after a delay of one
TCK
cycle. Note that the first
bit shifted out will be a zero. The bypass register is not affected in the UPDATE-DR state.
相關(guān)PDF資料
PDF描述
P60ARM-IG Low power, general purpose 32-bit RISC microprocessor
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相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
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