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| 型號(hào)： | P60ARM-GP1N |
| 廠(chǎng)商： | Zarlink Semiconductor Inc. |
| 英文描述： | Low power, general purpose 32-bit RISC microprocessor |
| 中文描述： | 低功耗，通用32位RISC微處理器 |
| 文件頁(yè)數(shù)： | 42/120頁(yè) |
| 文件大?。?/td> | 1275K |
| 代理商： | P60ARM-GP1N |
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P60ARM-B
38
Big Endian Configuration
A byte load (LDRB) expects the data on data bus inputs 31 through 24 if the supplied address is on a word
boundary, on data bus inputs 23 through 16 if it is a word address plus one byte, and so on. The selected
byte is placed in the bottom 8 bits of the destination register and the remaining bits of the register are filled
with zeros.
A byte store (STRB) repeats the bottom 8 bits of the source register four times across data bus outputs 31
through 0. The external memory system should activate the appropriate byte subsystem to store the data.
A word load (LDR) should generate a word aligned address. An address offset of 0 or 2 from a word
boundary will cause the data to be rotated into the register so that the addressed byte occupies bits 31
through 24. This means that half-words accessed at these offsets will be correctly loaded into bits 16 through
31 of the register. A shift operation is then required to move (and optionally sign extend) the data into the
bottom 16 bits. An address offset of 1 or 3 from a word boundary will cause the data to be rotated into the
register so that the addressed byte occupies bits 15 through 8.
A word store (STR) should generate a word aligned address. The word presented to the data bus is not
affected if the address is not word aligned. That is, bit 31 of the register being stored always appears on data
bus output 31.
4.7.4 Use of R15
Write-back shall not be specified if R15 is specified as the base register (Rn). When using R15 as the base
register you must remember it contains an address 8 bytes on from the address of the current instruction.
R15 shall not be specified as the register offset (Rm).
When R15 is the source register (Rd) of a register store (STR) instruction, the stored value will be address
of the instruction plus 12.
4.7.5 Restriction on the use of base register
When configured for late
aborts, the following example code is difficult to unwind as the base register, Rn,
gets updated before the
abort handler starts. Sometimes it may be impossible to calculate the initial value.
For example:
LDR
R0,[R1],R1
<LDR|STR> Rd, [Rn],{+/-}Rn{,<shift>}
Therefore a post-indexed LDR|STR where Rm is the same register as Rn shall not be used.
相關(guān)PDF資料 |
PDF描述 |
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| P60ARM-IG | Low power, general purpose 32-bit RISC microprocessor |
| P60ARM-B | Low power, general purpose 32-bit RISC microprocessor |
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| P60ARM-IG | 制造商:ZARLINK 制造商全稱(chēng):Zarlink Semiconductor Inc 功能描述:Low power, general purpose 32-bit RISC microprocessor |
| P-60AS/A18 | 功能描述:BATTERY NICAD 2/3A 600MAH W/TAB RoHS:否 類(lèi)別:電池產(chǎn)品 >> 電池，充電式（蓄電池） 系列:- MSDS 材料安全數(shù)據(jù)表:Nickel Metal Hydride Battery MSDS 標(biāo)準(zhǔn)包裝:1,000 系列:TWICELL 電池化學(xué):鎳金屬氫化物 電池大小:AAA 電壓 - 額定:1.2V 容量:930mAh 尺寸/尺寸:- 端接類(lèi)型:焊片 放電速率:186mA 標(biāo)準(zhǔn)充電電流:100mA 標(biāo)準(zhǔn)充電時(shí)間:16小時(shí) 重量:0.029 磅（13.15g） 裝運(yùn)信息:- 其它名稱(chēng):SY153T |
| P60AS302 | 制造商:APEM 功能描述: |
| P60AS632-8C | 制造商:NYLOK 功能描述: |
| P60AS701 | 功能描述:旋鈕開(kāi)關(guān) 10POS BCD 0.15A 24V RoHS:否 制造商:C&K Components 位置數(shù)量:5 卡片組數(shù)量: 每卡片組極數(shù):2 電流額定值:250 mA 電壓額定值:125 V 指數(shù)角: 觸點(diǎn)類(lèi)型: 觸點(diǎn)形式:DPST 端接類(lèi)型:Solder 安裝類(lèi)型:Panel 觸點(diǎn)電鍍:Silver |
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