參數(shù)資料
型號(hào): P60ARM-GP1N
廠商: Zarlink Semiconductor Inc.
英文描述: Low power, general purpose 32-bit RISC microprocessor
中文描述: 低功耗,通用32位RISC微處理器
文件頁數(shù): 90/120頁
文件大?。?/td> 1275K
代理商: P60ARM-GP1N
P60ARM-B
86
7.13 Coprocessor register transfer (Load from coprocessor)
Here the busy-wait cycles are much as above, but the transfer is limited to one data word, and ARM60 puts
the word into the destination register in the third cycle. The third cycle may be merged with the following
prefetch cycle into one memory N-cycle as with all ARM60 register load instructions. The cycle timings are
shown in
Table 19: Coprocessor register transfer (Load from coprocessor)
.
7.14 Coprocessor register transfer (Store to coprocessor)
As for the load from coprocessor, except that the last cycle is omitted. The cycle timings are shown below
in
Table 20: Coprocessor register transfer (Store to coprocessor)
.
Cycle
Address
nBW
nRW
Data
nMREQ
SEQ
nOPC
nCPI
CPA
CPB
ready
1
pc+8
1
0
(pc+8)
1
1
0
0
0
0
2
pc+12
1
0
CPdata
1
0
1
1
1
1
3
pc+12
1
0
-
0
1
1
1
-
-
pc+12
not ready
1
pc+8
1
0
(pc+8)
1
0
0
0
0
1
2
pc+8
1
0
CPdata
1
0
1
0
0
1
pc+8
1
0
-
1
0
1
0
0
1
n
pc+8
1
0
-
1
1
1
0
0
0
n+1
pc+12
1
0
CPdata
1
0
1
1
1
1
n+2
pc+12
1
0
-
0
1
1
1
-
-
pc+12
Table 19: Coprocessor register transfer (Load from coprocessor)
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