參數(shù)資料
型號(hào): P60ARM-GP1N
廠商: Zarlink Semiconductor Inc.
英文描述: Low power, general purpose 32-bit RISC microprocessor
中文描述: 低功耗,通用32位RISC微處理器
文件頁(yè)數(shù): 85/120頁(yè)
文件大?。?/td> 1275K
代理商: P60ARM-GP1N
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Instruction Cycle Operations
81
7.7 Store multiple registers
Store multiple proceeds very much as load multiple, without the final cycle. The restart problem is much
more straightforward here, as there is no wholesale overwriting of registers to contend with. The cycle
timings are shown in
Table 13: Store Multiple Registers Instruction Cycle Operations
.
7.8 Data swap
This is similar to the load and store register instructions, but the actual swap takes place in cycles 2 and 3.
In the second cycle, the data is fetched from external memory. In the third cycle, the contents of the source
register are written out to the external memory. The data read in cycle 2 is written into the destination
register during the fourth cycle. The cycle timings are shown below in
Table 14: Data Swap Instruction Cycle
Operations
.
The
LOCK
output of ARM60 is driven HIGH for the duration of the swap operation (cycles 2 & 3) to
indicate that both cycles should be allowed to complete without interruption.
The data swapped may be a byte or word quantity (b/w).
The swap operation may be
aborted in either the read or write cycle, and in both cases the destination
register will not be affected.
Cycle
Address
nBW
nRW
Data
nMREQ
SEQ
nOPC
1 register
1
pc+8
1
0
(pc+8)
0
0
0
2
alu
1
1
Ra
0
0
1
pc+12
n registers
1
pc+8
1
0
(pc+8)
0
0
0
(n>1)
2
alu
1
1
Ra
0
1
1
alu+
1
1
R
0
1
1
n
alu+
1
1
R
0
1
1
n+1
alu+
1
1
R
0
0
1
pc+12
Table 13: Store Multiple Registers Instruction Cycle Operations
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