參數(shù)資料
型號(hào): P60ARM-GP1N
廠商: Zarlink Semiconductor Inc.
英文描述: Low power, general purpose 32-bit RISC microprocessor
中文描述: 低功耗,通用32位RISC微處理器
文件頁數(shù): 58/120頁
文件大?。?/td> 1275K
代理商: P60ARM-GP1N
P60ARM-B
54
4.12 Coprocessor data
transfers (LDC, STC)
The instruction is only executed if the condition is true. The various conditions are defined at the beginning
of this chapter. The instruction encoding is shown in
Figure 26: Coprocessor Data Transfer Instructions
.
This class of instruction is used to load (LDC) or store (STC) a subset of a coprocessorss registers directly
to memory. ARM60 is responsible for supplying the memory address, and the coprocessor supplies or
accepts the data and controls the number of words transferred.
Figure 26: Coprocessor Data Transfer Instructions
4.12.1 The Coprocessor Telds
The CP# field is used to identify the coprocessor which is required to supply or accept the data, and a
coprocessor will only respond if its number matches the contents of this field.
The CRd field and the N bit contain information for the coprocessor which may be interpreted in different
ways by different coprocessors, but by convention CRd is the register to be transferred (or the first register
where more than one is to be transferred), and the N bit is used to choose one of two transfer length options.
For instance N=0 could select the transfer of a single register, and N=1 could select the transfer of all the
registers for context switching.
Cond
Rn
0
11
12
15
16
19
20
21
24
25
27
28
31
P U
W L
22
23
110
N
CRd
CP#
Offset
7
8
Coprocessor number
Coprocessor source/destination register
Unsigned 8 bit immediate offset
Base register
Load/Store bit
1 = Load from memory
Write-back bit
1 = write address into base
Transfer length
Pre/Post indexing bit
1 = pre; add offset before transfer
Up/Down bit
1 = up; add offset to base
Condition field
相關(guān)PDF資料
PDF描述
P60ARM-IG Low power, general purpose 32-bit RISC microprocessor
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相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
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