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| 型號(hào)： | P610ARM-B |
| 廠商： | Zarlink Semiconductor Inc. |
| 英文描述： | General purpose 32-bit microprocessor |
| 中文描述： | 通用32位微處理器 |
| 文件頁(yè)數(shù)： | 126/173頁(yè) |
| 文件大?。?/td> | 897K |
| 代理商： | P610ARM-B |
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Bus interface
ARM610 Data Sheet
10-2
10.1 Introduction
The ARM610 has two input clocks:
controlled by
MCLK
the operation being carried out. For example, if the core CPU is reading data from the
cache it will be clocked by
FCLK
, whereas if it is reading data from uncached external
memory it will be clocked by
MCLK
. The ARM610 control logic ensures that the correct
clock is used internally and automatically switches between the two clocks.
FCLK
and
MCLK
. The bus interface is always
. The core CPU switches between these two clocks according to
The ARM610 bus interface is designed to operate in synchronous mode. In this mode,
there is a tightly defined relationship between
make transitions on the falling edge of
FCLK
clocks is permitted, and the device will function correctly, but
than
FCLK
. Refer to
·
13.2 Relationship between FCLK and MCLK
FCLK
. An amount of jitter between the two
MCLK
and
MCLK
.
MCLK
may only
must not be later
on page 13-2.
10.2 ARM610 Cycle Speed
The bus interface is controlled by
respect to this clock. The speed of the memory may be controlled in one of two ways.
MCLK
, and all timing parameters are referenced with
1
The LOW and HIGH phases of the clock may be stretched.
2
nWAIT
this signal maintains the LOW phase of the cycle by gating out
may only change when
MCLK
is LOW.
can be used to insert entire
MCLK
cycles into the access. When LOW,
MCLK
.
nWAIT
10.3 Cycle Types
There are two basic cycle types performed by an ARM610. These are
memory
cycles. Idle cycles and memory cycles are combined to perform memory
accesses. The two cycle types are differentiated by the signal
inverse of
nMREQ
, and is provided for backwards compatibility with earlier memory
controllers).
nMREQ
HIGH indicates an idle cycle, and
memory access. However,
nMREQ
is pipelined, so that its value determines the type
of the following cycle.
nMREQ
becomes valid during the LOW phase of the cycle
before the one to which it refers.
idle
cycles and
nMREQ
. (
SEQ
is the
nMREQ
LOW indicates a
The address from ARM610 becomes valid during the HIGH phase of
pipelined, and its value refers to the following memory access.
MCLK
. It is also
10.4 Memory Access
There are two types of memory access. These are
nonsequential cycles occur when a new memory access takes place. A sequential
cycle occurs when:
nonsequential
and
sequential
. The
the cycle is of the same type as the previous cycle
the address is one word (four bytes) greater than the previous access
So for example, a single word access consists of a nonsequential access, and a
two-word access consists of a nonsequential access followed by a sequential access.
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| P610ARM-KG | General purpose 32-bit microprocessor |
| P610ARM-KW | General purpose 32-bit microprocessor |
| P6121-AU120 | Incremental Encoders |
| P6111-AP120 | Incremental Encoders |
| P6111-AP192 | Incremental Encoders |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| P610ARM-B/KG/FPNR | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:MICROPROCESSOR|32-BIT|CMOS|QFP|144PIN|PLASTIC |
| P610ARM-B/KW/FPNR | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:MICROPROCESSOR|32-BIT|CMOS|QFP|144PIN|PLASTIC |
| P610ARM-FPNR | 制造商:ZARLINK 制造商全稱:Zarlink Semiconductor Inc 功能描述:General purpose 32-bit microprocessor |
| P610ARM-KG | 制造商:ZARLINK 制造商全稱:Zarlink Semiconductor Inc 功能描述:General purpose 32-bit microprocessor |
| P610ARM-KW | 制造商:ZARLINK 制造商全稱:Zarlink Semiconductor Inc 功能描述:General purpose 32-bit microprocessor |
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