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參數(shù)資料
| 型號(hào)： | P610ARM-B |
| 廠商： | Zarlink Semiconductor Inc. |
| 英文描述： | General purpose 32-bit microprocessor |
| 中文描述： | 通用32位微處理器 |
| 文件頁(yè)數(shù)： | 43/173頁(yè) |
| 文件大小： | 897K |
| 代理商： | P610ARM-B |
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Instruction Set - TEQ, TST, CMP, CMN
ARM610 Data Sheet
4-15
O
4.4.3 Immediate operand rotates
The immediate operand rotate field is a 4-bit unsigned integer which specifies a shift
operation on the 8-bit immediate value. This value is zero extended to 32 bits, and then
subject to a rotate right by twice the value in the rotate field. This enables many
common constants to be generated, for example all powers of 2.
4.4.4 Writing to R15
When Rd is a register other than R15, the condition code flags in the CPSR may be
updated from the ALU flags as described above.
When Rd is R15 and the S flag in the instruction is not set the result of the operation
is placed in R15 and the CPSR is unaffected.
When Rd is R15 and the S flag is set the result of the operation is placed in R15 and
the SPSR corresponding to the current mode is moved to the CPSR. This allows state
changes which atomically restore both PC and CPSR. This form of instruction should
not be used in User mode.
4.4.5 Using R15 as an operand
If R15 (the PC) is used as an operand in a data processing instruction the register is
used directly.
The PC value will be the address of the instruction, plus 8 or 12 bytes due to instruction
prefetching. If the shift amount is specified in the instruction, the PC will be 8 bytes
ahead. If a register is used to specify the shift amount the PC will be 12 bytes ahead.
4.4.6 TEQ, TST, CMP and CMN opcodes
Note
TEQ, TST, CMP and CMN do not write the result of their operation but do set flags in
the CPSR. An assembler should always set the S flag for these instructions even if this
is not specified in the mnemonic.
The TEQP form of the TEQ instruction used in earlier ARM processors must not be
used: the PSR transfer operations should be used instead.
The action of TEQP in the ARM610 is to move SPSR_<mode> to the CPSR if the
processor is in a privileged mode and to do nothing if in User mode.
4.4.7 Assembler syntax
1
MOV,MVN (single operand instructions.)
<opcode>{cond}{S} Rd,<Op2>
2
CMP,CMN,TEQ,TST (instructions which do not produce a result.)
<opcode>{cond} Rn,<Op2>
3
AND,EOR,SUB,RSB,ADD,ADC,SBC,RSC,ORR,BIC
<opcode>{cond}{S} Rd,Rn,<Op2>
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| P610ARM-KG | General purpose 32-bit microprocessor |
| P610ARM-KW | General purpose 32-bit microprocessor |
| P6121-AU120 | Incremental Encoders |
| P6111-AP120 | Incremental Encoders |
| P6111-AP192 | Incremental Encoders |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| P610ARM-B/KG/FPNR | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:MICROPROCESSOR|32-BIT|CMOS|QFP|144PIN|PLASTIC |
| P610ARM-B/KW/FPNR | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:MICROPROCESSOR|32-BIT|CMOS|QFP|144PIN|PLASTIC |
| P610ARM-FPNR | 制造商:ZARLINK 制造商全稱:Zarlink Semiconductor Inc 功能描述:General purpose 32-bit microprocessor |
| P610ARM-KG | 制造商:ZARLINK 制造商全稱:Zarlink Semiconductor Inc 功能描述:General purpose 32-bit microprocessor |
| P610ARM-KW | 制造商:ZARLINK 制造商全稱:Zarlink Semiconductor Inc 功能描述:General purpose 32-bit microprocessor |
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