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參數(shù)資料
| 型號： | P610ARM-B |
| 廠商： | Zarlink Semiconductor Inc. |
| 英文描述： | General purpose 32-bit microprocessor |
| 中文描述： | 通用32位微處理器 |
| 文件頁數(shù)： | 127/173頁 |
| 文件大小： | 897K |
| 代理商： | P610ARM-B |
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Bus interface
ARM610 Data Sheet
10-3
Nonsequential accesses consist of an idle cycle followed by a memory cycle, and
sequential accesses consist simply of a memory cycle. In the case of a nonsequential
access, the address is valid throughout the idle cycle, allowing extra time for memory
decoding.
10.5 Read/Write
Memory accesses may be read or write, differentiated by the signal
has the same timing as the address, so is likewise pipelined, and refers to the following
cycle. In the case of a write, the ARM610 outputs data on the data bus during the
memory cycle. It becomes valid during
MCLK
cycle. In the case of a read, data is sampled at the end of the memory cycle.
not change during a sequential access, so if a read from address A is followed
immediately be a write to address (A+4), the write to address (A+4) will be a
nonsequential access.
nRW
. This signal
LOW, and is held until the end of the
nRW
may
10.6 Byte/Word
Likewise, any memory access may be of a word or a byte quantity. These are
differentiated by the signal
nBW
, which also has the same timing as the address, ie. it
becomes valid in the HIGH phase of
MCLK
refers.
nBW
LOW indicates a byte access. Again,
sequential accesses.
in the cycle before the one to which it
nBW
may not change during
10.7 Maximum Sequential Length
As explained above, the ARM610 will perform sequential memory accesses whenever
the cycle is of the same type (ie byte/word, read/write) as the previous cycle, and the
addresses are consecutive. However, sequential accesses are interrupted on a 256
word boundary. This is to allow the MMU to check the translation protection as the
address crosses a sub-page boundary. If a sequential access is performed over a 256
word boundary, the access to word 256 is simply turned into a nonsequential access,
and then further accesses continue sequentially as before.
Figure 10-1: One word read or write
MCLK
A[31:0]
nMREQ
WRITE
D[31:0]
D[31:0]
READ
相關PDF資料 |
PDF描述 |
|---|---|
| P610ARM-KG | General purpose 32-bit microprocessor |
| P610ARM-KW | General purpose 32-bit microprocessor |
| P6121-AU120 | Incremental Encoders |
| P6111-AP120 | Incremental Encoders |
| P6111-AP192 | Incremental Encoders |
相關代理商/技術參數(shù) |
參數(shù)描述 |
|---|---|
| P610ARM-B/KG/FPNR | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:MICROPROCESSOR|32-BIT|CMOS|QFP|144PIN|PLASTIC |
| P610ARM-B/KW/FPNR | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:MICROPROCESSOR|32-BIT|CMOS|QFP|144PIN|PLASTIC |
| P610ARM-FPNR | 制造商:ZARLINK 制造商全稱:Zarlink Semiconductor Inc 功能描述:General purpose 32-bit microprocessor |
| P610ARM-KG | 制造商:ZARLINK 制造商全稱:Zarlink Semiconductor Inc 功能描述:General purpose 32-bit microprocessor |
| P610ARM-KW | 制造商:ZARLINK 制造商全稱:Zarlink Semiconductor Inc 功能描述:General purpose 32-bit microprocessor |
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