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參數(shù)資料
| 型號(hào)： | P610ARM-B |
| 廠商： | Zarlink Semiconductor Inc. |
| 英文描述： | General purpose 32-bit microprocessor |
| 中文描述： | 通用32位微處理器 |
| 文件頁(yè)數(shù)： | 77/173頁(yè) |
| 文件大?。?/td> | 897K |
| 代理商： | P610ARM-B |
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Instruction Set - LDC, STC
ARM610 Data Sheet
4-49
O
4.13 Coprocessor Data
Transfers (LDC, STC)
The instruction is only executed if the condition is true. The various conditions are
defined in
·
Table 4-2: Condition code summaryon page 4-6. The instruction encoding
is shown in
·
Figure 4-24: Coprocessor data transfer instructions
This class of instruction is used to load (LDC) or store (STC) a subset of a
coprocessors’s registers directly to memory. ARM610 is responsible for supplying the
memory address, and the coprocessor supplies or accepts the data and controls the
number of words transferred.
Figure 4-24: Coprocessor data transfer instructions
4.13.1 The coprocessor fields
The CP# field is used to identify the coprocessor which is required to supply or accept
the data, and a coprocessor will only respond if its number matches the contents of
this field.
The CRd field and the N bit contain information for the coprocessor which may be
interpreted in different ways by different coprocessors, but by convention CRd is the
register to be transferred (or the first register where more than one is to be transferred),
and the N bit is used to choose one of two transfer length options. For instance N=0
could select the transfer of a single register, and N=1 could select the transfer of all the
registers for context switching.
31
28 27
25
24
23
22
21
20 19
16 15
12 11
8
7
0
Cond
1110
P
U
N
W
L
Rn
CRd
CP#
Offset
Unsigned 8-bit immediate offset
Coprocessor number
Coprocessor source/destination register
Base register
Load/Store bit
0 = Store to memory
1 = Load from memory
Write-back bit
0 = No write-back
1 = Write address into base
Transfer length
Up/Down bit
0 = Down; subtract offset from base
1 = Up; add offset to base
Pre/Post Indexing bit
0 = Post; add offset after transfer
1 = Pre; add offset before transfer
Condition field
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| P610ARM-KG | General purpose 32-bit microprocessor |
| P610ARM-KW | General purpose 32-bit microprocessor |
| P6121-AU120 | Incremental Encoders |
| P6111-AP120 | Incremental Encoders |
| P6111-AP192 | Incremental Encoders |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| P610ARM-B/KG/FPNR | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:MICROPROCESSOR|32-BIT|CMOS|QFP|144PIN|PLASTIC |
| P610ARM-B/KW/FPNR | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:MICROPROCESSOR|32-BIT|CMOS|QFP|144PIN|PLASTIC |
| P610ARM-FPNR | 制造商:ZARLINK 制造商全稱:Zarlink Semiconductor Inc 功能描述:General purpose 32-bit microprocessor |
| P610ARM-KG | 制造商:ZARLINK 制造商全稱:Zarlink Semiconductor Inc 功能描述:General purpose 32-bit microprocessor |
| P610ARM-KW | 制造商:ZARLINK 制造商全稱:Zarlink Semiconductor Inc 功能描述:General purpose 32-bit microprocessor |
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