參數(shù)資料
型號: P610ARM-B
廠商: Zarlink Semiconductor Inc.
英文描述: General purpose 32-bit microprocessor
中文描述: 通用32位微處理器
文件頁數(shù): 65/173頁
文件大?。?/td> 897K
代理商: P610ARM-B
Instruction Set - LDM, STM
ARM610 Data Sheet
4-37
O
4.9.2 Addressing modes
The transfer addresses are determined by the contents of the base register (Rn), the
pre/post bit (P) and the up/down bit (U). The registers are transferred in the order
lowest to highest, so R15 (if in the list) will always be transferred last. The lowest
register also gets transferred to/from the lowest memory address. By way of
illustration, consider the transfer of R1, R5 and R7 in the case where Rn=0x1000 and
write back of the modified base is required (W=1).
·
Figure 4-17: Post-increment
addressing
·
Figure 4-18: Pre-increment addressing
·
Figure 4-19: Post-decrement
addressingand
·
Figure 4-20: Pre-decrement addressingshow the sequence of
register transfers, the addresses used, and the value of Rn after the instruction has
completed.
In all cases, had write back of the modified base not been required (W=0), Rn would
have retained its initial value of 0x1000 unless it was also in the transfer list of a load
multiple register instruction, when it would have been overwritten with the loaded
value.
4.9.3 Address alignment
The address should normally be a word aligned quantity and non-word aligned
addresses do not affect the instruction. However, the bottom 2 bits of the address will
appear on
A[1:0]
and might be interpreted by the memory system.
Figure 4-17: Post-increment addressing
0x100C
0x1000
0x0FF4
Rn
1
0x100C
0x1000
0x0FF4
2
R1
0x100C
0x1000
0x0FF4
3
0x100C
0x1000
0x0FF4
4
R1
R7
R5
R1
R5
Rn
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