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參數(shù)資料
| 型號： | PC755BMZFU400LD |
| 英文描述： | MICROPROCESSOR|32-BIT|CMOS|BGA|360PIN|PLASTIC |
| 中文描述： | 微處理器| 32位|的CMOS | BGA封裝| 360PIN |塑料 |
| 文件頁數(shù)： | 22/48頁 |
| 文件大?。?/td> | 276K |
| 代理商： | PC755BMZFU400LD |
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22/48
PC755B/745B
Assuming an air velocity of 0.5 m/s, we have an effective R
sa
of 7
o
C/W, thus
T
j
= 30
o
C+ 5
o
C+ (0.03
o
C/W +1.0
o
C/W + 7
o
C/W) * 5.0 W,
resulting in a die-junction temperature of approximately 81
o
C which is well within the maximum operating temperature of the compo-
nent.
Other heat sinks offered by Chip Coolers, IERC, Thermalloy, Wakefield Engineering, and Aavid Engineering offer different heat sink-
to-ambient thermal resistances, and may or may not need air flow.
Though the die junction-to-ambient and the heat sink-to-ambient thermal resistances are a common figure-of-merit used for compar-
ing the thermal performance of various microelectronic packaging technologies, one should exercise caution when only using this
metric in determining thermal management because no single parameter can adequately describe three-dimensional heat flow. The
final die-junction operating temperature, is not only a function of the component-level thermal resistance, but the system-level design
and its operating conditions. In addition to the component’s power consumption, a number of factors affect the final operating die-junc-
tion temperature—airflow, board population (local heat flux of adjacent components), heat sink efficiency, heat sink attach, heat sink
placement, next-level interconnect technology, system air temperature rise, altitude, etc.
Due to the complexity and the many variations of system-level boundary conditions for today’s microelectronic equipment, the com-
bined effects of the heat transfer mechanisms (radiation, convection and conduction) may vary widely. For these reasons, we recom-
mend using conjugate heat transfer models for the board, as well as, system-level designs. To expedite system-level thermal analy-
sis, several “compact” thermal-package models are available within FLOTHERM
. These are available upon request.
3.5. Power consideration
3.5.1. Power management
The PC755B provides four power modes, selectable by setting the appropriate control bits in the MSR and HIDO registers. The four
power modes are as follows :
Full-power: This is the default power state of the PC755B. The PC755B is fully powered and the internal functional units are operat-
ing at the full processor clock speed. If the dynamic power management mode is enabled, functional units that are idle will automat-
ically enter a low-power state without affecting performance, software execution, or external hardware.
Doze: All the functional units of the PC755B are disabled except for the time base/decrementer registers and the bus snooping
logic. When the processor is in doze mode, an external asynchronous interrupt, a system management interrupt, a decrementer
exception, a hard or soft reset, or machine check brings the PC755B into the full-power state. The PC755B in doze mode maintains
the PLL in a fully powered state and locked to the system external clock input (SYSCLK) so a transition to the full-power state takes
only a few processor clock cycles.
Nap: The nap mode further reduces power consumption by disabling bus snooping, leaving only the time base register and the
PLL in a powerred state. The PC755B returns to the full-power state upon receipt of an external asynchronous interrupt, a system
management interrupt, a decrementer exception, a hard or soft reset, or a machine check input (MCP). A return to full-power state
from a nap state takes only a few processor clock cycles. When the processor is in nap mode, if QACK is negated, the processor
is put in doze mode to support snooping.
Sleep: Sleep mode minimizes power consumption by disabling all internal functional units, after which external system logic may
disable the PPL and SUSCLK. Returning the PC755B to the full-power state requires the enabling of the PPL and SYSCLK, fol-
lowed by the assertion of an external asynchronous interrupt, a system management interrupt, a hard or soft reset, or a machine
check input (MCP) signal after the time required to relock the PPL.
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