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| 型號： | PC755BMZFU400LD |
| 英文描述： | MICROPROCESSOR|32-BIT|CMOS|BGA|360PIN|PLASTIC |
| 中文描述： | 微處理器| 32位|的CMOS | BGA封裝| 360PIN |塑料 |
| 文件頁數(shù)： | 29/48頁 |
| 文件大?。?/td> | 276K |
| 代理商： | PC755BMZFU400LD |
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PC755B/745B
29/48
Table 13. L2CLK Output AC Timing Specification
At Vdd=AVdd=2.0V 100mV; -55
Tj
+125
o
C, OVdd = 3.3V 165mV and OVdd = 1.8V 100mV and OVdd = 2.0V 100mV
Parameter
Symbol
300,350,400 MHz
Unit
Notes
Min
Max
L2CLK frequency
f
L2CLK
80
400
MHz
1,4
L2CLK cycle time
t L2CLK
2,5
12.5
ns
L2CLK duty cycle
tCHCL/tL2CLK
50
%
2,7
Internal DLL-relock time
640
—
L2CLK
3,7
DLL capture window
0
10
ns
5,7
L2CLKOUT output-to-output skew
t
L2CSKW
50
ps
6,7
L2CLKOUT output jitter
150
ps
6,7
Notes:
1. L2CLK outputs are L2CLK_OUTA, L2CLK_OUTB, L2CLK_OUT and L2SYNC_OUT pins. The L2CLK frequency to core fre-
quency settings must be chosen such that the resulting L2CLK frequency and core frequency do not exceed their respective
maximum or minimum operating frequencies. The maximum L2LCK frequency will be system dependent. L2CLK_OUTA and
L2CLK_OUTB must have equal loading.
2. The nominal duty cycle of the L2CLK is 50% measured at midpoint voltage.
3. The DLL re-lock time is specified in terms of L2CLKs. The number in the table must be multiplied by the period of L2CLK to com-
pute the actual time duration in nanoseconds. Re-lock timing is guaranteed by design and characterization.
4. The L2CR[L2SL] bit should be set for L2CLK frequencies less than 110 MHz. This adds more delay to each tap of the DLL.
5. Allowable skew between L2SYNC_OUT and L2SYNC_IN.
6. This output jitter number represents the maximum delay of one tap forward or one tap back from the current DLL tap as the phase
comparator seeks to minimize the phase difference between L2SYNC_IN and the internal L2CLK. This number must be compre-
hended in the L2 timing analysis. The input jitter on SYSCLK affects L2CLKOUT and the L2 address/data/control signals equally
and therefore is already comprehended in the AC timing and does not have to be considered in the L2 timing analysis.
7. Guaranteed by design and characterization.
The L2CLK_OUT timing diagram is shown in Figure 14.
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