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參數資料
| 型號： | PC755BMZFU400LD |
| 英文描述： | MICROPROCESSOR|32-BIT|CMOS|BGA|360PIN|PLASTIC |
| 中文描述： | 微處理器| 32位|的CMOS | BGA封裝| 360PIN |塑料 |
| 文件頁數： | 27/48頁 |
| 文件大?。?/td> | 276K |
| 代理商： | PC755BMZFU400LD |
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PC755B/745B
27/48
Figure 11 provides the mode select input timing diagram for the PC755B.
HRESET
MODE SIGNALS
tMVRH
tMXRH
VM = Midpoint Voltage (OVDD/2)
VM
Figure 11 : Mode Input Timing Diagram
Figure 12 provides the AC test load for the PC755B.
OUTPUT
OVdd/2
RL = 5
Z0 = 50
Figure 12 : AC Test Load
Table 12. Processor Bus AC Timing Specifications
At Vdd=AVdd=2.0V 100mV; -55
Tj
+125
o
C, OVdd = 3.3V
165mV and OVdd = 1.8V 100mV and OVdd = 2.0V 100mV
Parameter
Symbols
300, 350, 400 MHz
Unit
Notes
Min
Max
Setup Times: All Inputs
t
IVKH
2.5
—
ns
Input Hold Times: All Inputs
t
IXKH
0.6
—
ns
Valid Times: All Outputs
t
KHOV
—
4.5
ns
Output Hold Times: All Outputs
t
KHOX
1.0
—
ns
SYSCLK to Output Enable
t
KHOE
0.5
—
ns
4
SYSCLK to Output High Impedance (all except ABB, ARTRY, DBB)
t
KHOZ
—
6.0
ns
4
SYSCLK to ABB, DBB High Impedance after precharge
t
KHABPZ
—
1.0
t
sysclk
1,2,4
Maximum Delay to ARTRY Precharge
t
KHARP
—
1
t
sysclk
1,3,4
SYSCLK to ARTRY High Impedance After Precharge
t
KHARPZ
—
2
t
sysclk
1,3,4
Notes:
1. t
sysclk
is the period of the external clock (SYSCLK) in nanoseconds (ns). The numbers given in the table must be multiplied by the
period of SYSCLK to compute the actual time duration (in nanoseconds) of the parameter in question.
2. Per the 60x bus protocol, TS, ABB and DBB are driven only by the currently active bus master. They are asserted low then pre-
charged high before returning to high-Z as shown in Figure 13. The nominal precharge width for TS, ABB or DBB is 0.5* t
SYSCLK
,
i.e. less than the minimum t
SYSCLK
period, to ensure that another master asserting TS, ABB, or DBB on the following clock will not
contend with the precharge. Output valid and output hold timing is tested for the signal asserted. Output valid time is tested for pre-
charge.The high-Z behavior is guaranteed by design.
3. Per the 60x bus protocol, ARTRY can be driven by multiple bus masters through the clock period immediately following AACK. Bus
contention is not an issue since any master asserting ARTRY will be driving it low. Any master asserting it low in the first clock follow-
ing AACK will then go to high-Z for one clock before precharging it high during the second cycle after the assertion of AACK. The
nominal precharge width for ARTRY is 1.0 t
sysclk
; i.e. it should be high-Z as shown in Figure 12 before the first opportunity for another
master to assert ARTRY. Output valid and output hold timing is tested for the signal asserted. Output valid time is tested for prechar-
ge.The high-Z and precharge behavior is guaranteed by design.
4. Guaranteed by design and characterization.
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