參數(shù)資料
型號: PC755BMZFU400LD
英文描述: MICROPROCESSOR|32-BIT|CMOS|BGA|360PIN|PLASTIC
中文描述: 微處理器| 32位|的CMOS | BGA封裝| 360PIN |塑料
文件頁數(shù): 45/48頁
文件大?。?/td> 276K
代理商: PC755BMZFU400LD
PC755B/745B
45/48
Figure 30 describes the alternate driver impedance measurement circuit.
(L2)OVdd
BGA
Pin
Data
Vforce
OGND
Figure 30 : Alternate Driver Impedance Measurement Curcuit
Table 19 summarizes the signal impedance results. The driver impedance values were characterized at 0 C, 65 C, and 105 C. The
impedance increases with junction temperature and is relatively unaffected by bus voltage.
Table 19. Impedance Characteristics
Vdd = 2.0V, OVdd = 3.3V, Tc = 0 - 105 C
Impedance
Processor bus
L2 bus
Symbol
Unit
R
N
25-36
25-36
Z
0
Ohms
R
P
26-39
26-39
Z
0
Ohms
9.6. Pull-up Resistor Requirements
The PC755B requires high-resistive (weak: 10 K
) pull-up resistors on several control pins of the bus interface to maintain the control
signals in the negated state after they have been actively negated and released by the PC755B or other bus masters. These pins are
TS, ABB, ARTRY.
In addition, the PC755B has one open-drain style output that requires a pull-up resistor (weak or stronger: 4.7 K
W
–10 K
W
) if it is
used by the system. This pin is CKSTP_OUT.
During inactive periods on the bus, the address and transfer attributes may not be driven by any master and may therefore float in the
high-impedance state for relatively long periods of time. Since the PC755B must continually monitor these signals for snooping, this
float condition may cause excessive power draw by the input receivers on the PC755B or by other receivers in the system. It is recom-
mended that these signals be pulled up through weak (10 K
)
pull-up resistors by the system, or that they may be otherwise driven by
the system during inactive periods of the bus. The snooped address and transfer attribute inputs are:
A[0:31], AP[0:3], TT[0:4], TBST and GBL.
The data bus input receivers are normally turned off when no read operation is in progress and therefore do not require pull-up resis-
tors on the bus. Other data bus receivers in the system, however, may require pullups, or that those signals be otherwise driven by the
system during inactive periods by the system. The data bus signals are: DH[0:31],DL[0:31] andDP[0:7]
If 32-bit data bus mode is selected, the input receivers of the unused data and parity bits will be disabled, and their outputs will drive
logic zeros when they would otherwise normally be driven. For this mode, these pins do not require pull-up resistors, and should be left
unconnected by the system to minimize possible output switching.
If address or data parity is not used by the system, and the respective parity checking is disabled through HID0, the input receivers for
those pins are disabled, and those pins do not require pull-up resistors and should be left unconnected by the system. If all parity
generation is disabled through HID0, then all parity checking should also be disabled through HID0, and all parity pins may be left
unconnected by the system.
The L2 interface does not normally require pull-up resistors.
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