參數(shù)資料
型號(hào)： PC755BMZFU400LD
英文描述： MICROPROCESSOR|32-BIT|CMOS|BGA|360PIN|PLASTIC
中文描述： 微處理器| 32位|的CMOS | BGA封裝| 360PIN |塑料
文件頁(yè)數(shù)： 43/48頁(yè)
文件大小： 276K
代理商： PC755BMZFU400LD
PC755B/745B
43/48
9. SYSTEM DESIGN INFORMATION
9.1. PLL Power Supply Filtering
The AVdd and L2AVdd power signals are provided on the PC755B to provide power to the clock generation phase-locked loop and L2
cache delay-locked loop respectively. To ensure stability of the internal clock, the power supplied to the AVdd input signal should be
filtered of any noise in the 500kHz to 10MHz resonant frequency range of the PLL. A circuit similar to the one shown in Figure 27 using
surface mount capacitors with minimum Effective Series Inductance (ESL) is recommended. Consistent with the recommendations
of Dr. Howard Johnson in High Speed Digital Design: A Handbook of Black Magic Prentice Hall, 1993), multiple small capacitors of
equal value are recommended over a single large value capacitor.
The circuit should be placed as close as possible to the AVdd pin to minimize noise coupled from nearby circuits. An identical but
separate circuit should be placed as close as possible to the L2AVdd pin. It is often possible to route directly from the capacitors to the
AVdd pin, which is on the periphery of the 360 BGA footprint, without the inductance of vias. The L2AVdd pin may be more difficult to
route but is proportionately less critical.
Vdd
AVdd (or L2AVdd)
GND
Low ESL surface mount capacitors
2.2
μ
F
2.2
μ
F
10
Figure 27 : PLL Power Supply Filter Circuit
9.2. Power Supply Voltage Sequencing
The notes in Figure 28 contain cautions about the sequencing of the external bus voltages and core voltage of the PC755B (when
they are different). These cautions are necessary for the long term reliability of the part. If they are violated, the ESD (Electrostatic
Discharge) protection diodes will be forward biased and excessive current can flow through these diodes. If the system power supply
design does not control the voltage sequencing, the circuit of Figure 28 can be added to meet these requirements. The MUR420
Schottky diodes of Figure 28 control the maximum potential difference between the external bus and core power supplies on pow-
er-up and the 1N5820 diodes regulate the maximum potential difference on power-down.
3.3V
2.0V
MUR420
1N5820
MUR420
MUR420
1N5820
Figure 28 : Example Voltage Sequencing Circuit
9.3. Decoupling Recommendations
Due to the PC755B’s dynamic power management feature, large address and data buses, and high operating frequencies, the
PC755B can generate transient power surges and high frequency noise in its power supply, especially while driving large capacitive
loads. This noise must be prevented from reaching other components in the PC755B system, and the PC755B itself requires a clean,
tightly regulated source of power. Therefore, it is recommended that the system designer place at least one decoupling capacitor at
each Vdd, OVdd, and L2OVdd pin of the PC755B. It is also recommended that these decoupling capacitors receive their power from
separate Vdd, (L2)OVdd and GND power planes in the PCB, utilizing short traces to minimize inductance.
These capacitors should have a value of 0.01
μ
F or 0.1
μ
F. Only ceramic SMT (surface mount technology) capacitors should be used
to minimize lead inductance, preferably 0508 or 0603 orientations where connections are made along the length of the part.
In addition, it is recommended that there be several bulk storage capacitors distributed around the PCB, feeding the Vdd, L2OVdd,
and OVdd planes, to enable quick recharging of the smaller chip capacitors. These bulk capacitors should have a low ESR (equiva-
lent series resistance) rating to ensure the quick response time necessary. They should also be connected to the power and ground
planes through two vias to minimize inductance. Suggested bulk capacitors—100-330
μ
F (AVX TPS tantalum or Sanyo OSCON).
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