![](http://datasheet.mmic.net.cn/330000/PCI4515_datasheet_16443874/PCI4515_103.png)
51
5 ExCA Compatibility Registers (Function 0)
The ExCA (exchangeable card architecture) registers implemented in the PCI4515 controller are register-compatible
with the Intel 82365SL-DF PCMCIA controller. ExCA registers are identified by an offset value, which is compatible
with the legacy I/O index/data scheme used on the Intel
82365 ISA controller. The ExCA registers are accessed
through this scheme by writing the register offset value into the index register (I/O base), and reading or writing the
data register (I/O base + 1). The I/O base address used in the index/data scheme is programmed in the PC Card 16-bit
I/F legacy mode base address register. The offsets from this base address run contiguously from 00h to 3Fh for socket
A. See Figure 51 for an ExCA I/O mapping illustration. Table 51 identifies each ExCA register and its respective
ExCA offset.
The PCI4515 controller also provides a memory-mapped alias of the ExCA registers by directly mapping them into
PCI memory space. They are located through the CardBus socket registers/ExCA registers base address register
(PCI register 10h) at memory offset 800h. See Figure 52 for an ExCA memory mapping illustration. Note that
memory offsets are 800h844h for function 0. This illustration also identifies the CardBus socket register mapping,
which is mapped into the same 4K window at memory offset 0h.
The interrupt registers in the ExCA register set, as defined by the 82365SL specification, control such card functions
as reset, type, interrupt routing, and interrupt enables. Special attention must be paid to the interrupt routing registers
and the host interrupt signaling method selected for the PCI4515 controller to ensure that all possible PCI4515
interrupts can potentially be routed to the programmable interrupt controller. The ExCA registers that are critical to
the interrupt signaling are at memory address ExCA offsets 803h and 805h.
Access to I/O mapped 16-bit PC Cards is available to the host system via two ExCA I/O windows. These are regions
of host I/O address space into which the card I/O space is mapped. These windows are defined by start, end, and
offset addresses programmed in the ExCA registers described in this chapter. I/O windows have byte granularity.
Access to memory-mapped 16-bit PC Cards is available to the host system via five ExCA memory windows. These
are regions of host memory space into which the card memory space is mapped. These windows are defined by start,
end, and offset addresses programmed in the ExCA registers described in this chapter. Memory windows have
4-Kbyte granularity.
A bit location followed by a
means that this bit is not cleared by the assertion of PRST. This bit is only cleared by
the assertion of GRST. This is necessary to retain device context during the transition from D3 to D0.