![](http://datasheet.mmic.net.cn/330000/PCI4515_datasheet_16443874/PCI4515_51.png)
313
Table 39. EEPROM Loading Map (Continued)
SERIAL ROM
OFFSET
BYTE DESCRIPTION
25h
PCI 2Ch, subsystem vendor ID, byte 0
26h
PCI 2Dh, subsystem vendor ID, byte 1
27h
PCI 2Eh, subsystem ID, byte 0
28h
PCI 2Fh, subsystem ID, byte 1
29h
PCI F4h, Link_Enh, byte 0, bits 7, 2, 1
OHCI 50h, host controller control, bit 23
[7]
Link_Enh.
enab_unfair
[6]
HCControl.Program Phy Enable
[5:3]
RSVD
[2]
Link_Enh, bit 2
[1]
Link_Enh.
enab_accel
[0]
RSVD
2Ah
Mini-ROM address, this byte indicates the MINI ROM offset into the EEPROM
00h = No MINI ROM
Other Values = MINI ROM offset
2Bh
OHCI 24h, GUIDHi, byte 0
2Ch
OHCI 25h, GUIDHi, byte 1
2Dh
OHCI 26h, GUIDHi, byte 2
2Eh
OHCI 27h, GUIDHi, byte 3
2Fh
OHCI 28h, GUIDLo, byte 0
30h
OHCI 29h, GUIDLo, byte 1
31h
OHCI 2Ah, GUIDLo, byte 2
32h
OHCI 2Bh, GUIDLo, byte 3
33h
Checksum (Reserved—no bit loaded)
34h
PCI F5h, Link_Enh, byte 1, bits 7, 6, 5, 4
35h
PCI F0h, PCI miscellaneous, byte 0, bits 5, 4, 2, 1, 0
36h
PCI F1h, PCI miscellaneous, byte 1, bits 7, 3, 2, 1, 0
37h
Reserved
38h
Reserved (CardBus CIS pointer)
39h
Reserved
3Ah
PCI ECh, PCI PHY control, bits 7, 3, 1
3.7
Programmable Interrupt Subsystem
Interrupts provide a way for I/O devices to let the microprocessor know that they require servicing. The dynamic
nature of PC Cards and the abundance of PC Card I/O applications require substantial interrupt support from the
PCI4515 controller. The PCI4515 controller provides several interrupt signaling schemes to accommodate the needs
of a variety of platforms. The different mechanisms for dealing with interrupts in this controller are based on various
specifications and industry standards. The ExCA register set provides interrupt control for some 16-bit PC Card
functions, and the CardBus socket register set provides interrupt control for the CardBus PC Card functions. The
PCI4515 controller is, therefore, backward compatible with existing interrupt control register definitions, and new
registers have been defined where required.
The PCI4515 controller detects PC Card interrupts and events at the PC Card interface and notifies the host controller
using one of several interrupt signaling protocols. To simplify the discussion of interrupts in the PCI4515 controller,
PC Card interrupts are classified either as card status change (CSC) or as functional interrupts.
The method by which any type of PCI4515 interrupt is communicated to the host interrupt controller varies from
system to system. The PCI4515 controller offers system designers the choice of using parallel PCI interrupt signaling,
parallel ISA-type IRQ interrupt signaling, or the IRQSER serialized ISA and/or PCI interrupt protocol. It is possible
to use the parallel PCI interrupts in combination with either parallel IRQs or serialized IRQs, as detailed in the sections
that follow. All interrupt signaling is provided through the seven multifunction terminals, MFUNC0MFUNC6.