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參數(shù)資料
| 型號(hào)： | PCI4515ZHK |
| 廠商： | Texas Instruments, Inc. |
| 英文描述： | SINGLE SOCKET CARDBUS CONTROLLER WITH INTEGRATED |
| 中文描述： | 單插槽CardBus控制器，它集成 |
| 文件頁(yè)數(shù)： | 41/216頁(yè) |
| 文件大?。?/td> | 1138K |
| 代理商： | PCI4515ZHK |
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33
PCI LOCK indicates an atomic operation that may require multiple transactions to complete. When LOCK is asserted,
nonexclusive transactions can proceed to an address that is not currently locked. A grant to start a transaction on
the PCI bus does not assure control of LOCK; control of LOCK is obtained under its own protocol. It is possible for
different initiators to use the PCI bus while a single master retains ownership of LOCK. Note that the CardBus signal
for this protocol is CBLOCK to avoid confusion with the bus clock.
An agent may need to do an exclusive operation because a critical access to memory might be broken into several
transactions, but the master wants exclusive rights to a region of memory. The granularity of the lock is defined by
PCI to be 16 bytes, aligned. The LOCK protocol defined by the
PCI Local Bus Specification
allows a resource lock
without interfering with nonexclusive real-time data transfer, such as video.
The PCI bus arbiter may be designed to support only complete bus locks using the LOCK protocol. In this scenario,
the arbiter does not grant the bus to any other agent (other than the LOCK master) while LOCK is asserted. A
complete bus lock may have a significant impact on the performance of the video. The arbiter that supports complete
bus LOCK must grant the bus to the cache to perform a writeback due to a snoop to a modified line when a locked
operation is in progress.
The PCI4515 controller supports all LOCK protocols associated with PCI-to-PCI bridges, as also defined for
PCI-to-CardBus bridges. This includes disabling write posting while a locked operation is in progress, which can solve
a potential deadlock when using devices such as PCI-to-PCI bridges. The potential deadlock can occur if a CardBus
target supports delayed transactions and blocks access to the target until it completes a delayed read. This target
characteristic is prohibited by the
PCI Local Bus Specification
, and the issue is resolved by the PCI master using
LOCK.
3.4.4
Serial EEPROM I
2
C Bus
The PCI4515 controller offers many choices for modes of operation, and these choices are selected by programming
several configuration registers. For system board applications, these registers are normally programmed through the
BIOS routine. For add-in card and docking-station/port-replicator applications, the PCI4515 controller provides a
two-wire inter-integrated circuit (IIC or I
2
C) serial bus for use with an external serial EEPROM.
The PCI4515 controller is always the bus master, and the EEPROM is always the slave. Either device can drive the
bus low, but neither device drives the bus high. The high level is achieved through the use of pullup resistors on the
SCL and SDA signal lines. The PCI4515 controller is always the source of the clock signal, SCL.
System designers who wish to load register values with a serial EEPROM must use pullup resistors on the SCL and
SDA terminals. If the PCI4515 controller detects a logic-high level on the SCL terminal at the end of GRST, then it
initiates incremental reads from the external EEPROM. Any size serial EEPROM up to the I
2
C limit of 16 Kbits can
be used, but only the first 96 bytes (from offset 00h to offset 5Fh) are required to configure the PCI4515 controller.
Figure 33 shows a serial EEPROM application.
In addition to loading configuration data from an EEPROM, the PCI4515 I
2
C bus can be used to read and write from
other I
2
C serial devices. A system designer can control the I
2
C bus, using the PCI4515 controller as bus master, by
reading and writing PCI configuration registers
. Setting bit 3 (SBDETECT) in the serial bus control/status register (PCI
offset B3h, see Section 4.49) causes the PCI4515 controller to route the SDA and SCL signals to the SDA and SCL
terminals, respectively. The read/write data, slave address, and byte addresses are manipulated by accessing the
serial bus data, serial bus index, and serial bus slave address registers (PCI offsets B0h, B1h, and B2h; see Sections
4.46, 4.47, and 4.48, respectively).
EEPROM interface status information is communicated through the serial bus control and status register (PCI offset
B3h, see Section 4.49). Bit 3 (SBDETECT) in this register indicates whether or not the PCI4515 serial ROM circuitry
detects the pullup resistor on SCL. Any undefined condition, such as a missing acknowledge, results in bit 0
(ROM_ERR) being set. Bit 4 (ROMBUSY) is set while the subsystem ID register is loading (serial ROM interface is
busy).
The subsystem vendor ID for function 2 is also loaded through EEPROM. The EEPROM load data goes to all three
functions from the serial EEPROM loader.
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| PCI6420 | Integrated 2-Slot PC Card & Dedicated Flash Media Controller |
| PCI6421 | DUAL/SINGLE SOCKET CARDBUS AND ULTRAMEDIA CONTROLLER |
| PCI6611 | DUAL/SINGLE SOCKET CARDBUS AND ULTRAMEDIA CONTROLLER |
| PCI6621 | DUAL/SINGLE SOCKET CARDBUS AND ULTRAMEDIA CONTROLLER |
| PCI6515 | SINGLE SOCKET CARDBUS CONTROLLER WITH DEDICATED SMART CARD SOCKET |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| PCI4520 | 制造商:TI 制造商全稱:Texas Instruments 功能描述:DUAL-SOCKET PC CARD AND INTEGRATED 1394A-2000 OHCI TWO-PORT PHY/LINK-LAYER CONTROLLER |
| PCI4520GHK | 功能描述:外圍驅(qū)動(dòng)器與原件 - PCI 2 Slot PC Card & int 1394a-2000 RoHS:否 制造商:PLX Technology 工作電源電壓: 最大工作溫度: 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FCBGA-1156 封裝:Tray |
| PCI4520ZHK | 制造商:Texas Instruments 功能描述: |
| PCI-471LF | 制造商:PROTECHSYSTEMS 制造商全稱:PROTECHSYSTEMS 功能描述:PCI ULV Celeron M CPU Card |
| PCI5 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Fuse |
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